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HP0-660 - NonStop Kernel Basics (Level 1) - Dump Information

Vendor : HP
Exam Code : HP0-660
Exam Name : NonStop Kernel Basics (Level 1)
Questions and Answers : 154 Q & A
Updated On : November 14, 2018
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HP0-660 Questions and Answers

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HP0-660 NonStop Kernel Basics (Level 1)

Study Guide Prepared by HP Dumps Experts HP0-660 Dumps and Real Questions

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HP0-660 exam Dumps Source : NonStop Kernel Basics (Level 1)

Test Code : HP0-660
Test Name : NonStop Kernel Basics (Level 1)
Vendor Name : HP
Q&A : 154 Real Questions

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HP HP NonStop Kernel Basics

HP says Itanium, HP-UX not dead yet | Real Questions and Pass4sure dumps

reader comments Share this story
  • at last week's crimson Hat Summit in Boston, Hewlett-Packard vice chairman for trade-commonplace Servers and software Scott Farrand become caught without PR minders by means of ServerWatch's Sean Michael Kerner, and can have slipped off message a little. In a video interview, Farrand said that HP changed into moving its strategy for mission-critical methods far from the Itanium processor and the HP-UX working system and toward x86-based mostly servers and purple Hat commercial enterprise Linux (RHEL), through a mission to carry business-critical performance to the Linux operating device referred to as assignment Dragon Hawk, itself a subset of HP's assignment Odyssey.

    task Dragon Hawk is an effort to bring the high-availability aspects of HP-UX, akin to ServiceGuard (which has already been ported to Linux) to RHEL and the Intel x86 platform with a mix of server firmware and utility. Dragon Hawk servers will run RHEL 6 and supply the means to partition processors into as much as 32 isolated virtual machines—a expertise pulled from HP-UX's technique useful resource manager. Farrand talked about that HP became positioning Dragon Hawk as its future mission-critical platform. "We definitely guide (Itanium and HP-UX) and love all that, however going ahead our method for mission-critical computing is moving to an x86 world," Farrand told Kernel. "it's not by using twist of fate that individuals have de-committed to Itanium, peculiarly Oracle."

    HP vice chairman Scott Farrand, interviewed at pink Hat Summit by means of Sean Michael Kerner of ServerWatch

    considering HP is still waiting for judgement in its case towards Oracle, that statement can also have made a couple of individuals in HP's business critical programs unit choke on their morning espresso. And sources at HP say that Farrand drifted slightly off-course in his feedback. The business's reputable line on mission Odyssey is that it is in parallel to and complementary to the enterprise's investments in Itanium and HP-UX. A source at HP noted Farrand disregarded a part of HP's challenge Odyssey briefing notes to that impact: "undertaking Odyssey contains persisted investment in our centered mission-essential portfolio of Integrity, NonStop, HP-UX, OpenVMS as well as our investments in constructing future mission-important x86 systems. delivering Serviceguard for Linux/x86 is a step towards reaching that mission-crucial x86 portfolio."

    undertaking Odyssey, youngsters, is HP's clear street forward with shoppers that haven't bought into HP-UX during the past. without a help for Itanium previous purple Hat Enterprse Linux version 5, and with RHEL being increasingly crucial to HP's method for cloud computing (and, pending litigation, support for Oracle on HP servers), in all probability Farrand become just a little bit forward of the company in his pronouncement.

    Tip of the hat to Ars reader Caveira for his tip on the ServerWatch story.


    HP Linux servers bolster NYSE buying and selling app | Real Questions and Pass4sure dumps

    during the last yr, NYSE has implemented some 200 new rack-based mostly HP ProLiant DL585 servers, about 400 ProLiant BL685c server blades and a few HP Integrity NonStop fault-tolerant servers for its three East Coast information centers.

    In a rare glimpse right into a mission-important Wall highway IT operation, the ny stock exchange (NYSE) has tested that it recently bought roughly 600 Hewlett-Packard Co. servers in aid of its Linux-based online buying and selling device.

    NYSE delivered the digital trading system, the NYSE Hybrid Market, in October 2006 to allow buyers to purchase and promote stocks on the buying and selling room flooring and by the use of the internet. The NYSE Hybrid Market now handles greater than 500 million messages a day, requiring extra servers and storage, referred to Steve Rubinow, the executive tips officer at NYSE.

    To accommodate the on-line buying and selling system, NYSE commissioned HP to change historical server and storage infrastructure.

    the entire blade servers and the ProLiant DL585s are in keeping with advanced Micro contraptions Inc. (AMD) dual-core processors, which are upgradeable to quad-core.

    The choice-making processBack in may additionally, NYSE also began migrating off a 1,600 million-guidelines-per-2nd (MIPS) mainframe to IBM equipment p servers running AIX.

    before determining HP, Rubinow considered solar Microsystems Inc. and IBM Corp. however he went with HP since it offered the optimal hardware options and service, he talked about.

    With the brand new HP servers, the average alternate-execution turnaround time has been decreased from seconds to milliseconds. The Hybrid Market now allows for as much as 1 million shares to be traded in a single order – up from 1,099 – due to the brand new server implementations and quicker interconnects, observed Paul Miller, HP's VP of server and storage advertising and marketing.

    The HP servers connect with 200 terabytes of HP StorageWorks XP12000 storage arrays, and the servers and storage are managed with HP's OpenView management tool, Miller mentioned.

    Free OS handles billions in stock tradesNYSE's significant functions consist of the trading methods that fit consumers and agents, transaction reporting programs, and regulatory surveillance systems, most of which run on Linux.

    moreover working Linux on its x86 bins, for the past 30 years NYSE has been an HP NonStop server user which runs the proprietary NonStop Kernel OS and additionally makes use of sun Microsystems' Solaris for legacy functions.

    "we've heaps of servers, and we are trying to architect our purposes to make them greater efficient, which starts with the software," Rubinow said. "you probably have inefficient application, you grow to be throwing more hardware at it."

    NYSE uses Linux because it's a greater bendy and low in cost operating equipment than most different alternate options, in accordance with Rubinow.

    "We want Linux for what we do. We don't want to be beholden to anybody [hardware or software] business enterprise, despite the fact that it is very first rate. We desire the liberty to be supplier-unbiased, so Linux was a good selection," noted Rubinow.

    Solaris for x86 is additionally used because it can run on a variety of servers, including HP's, he noted.

    Open source no problemNYSE adheres to the U.S. Securities and exchange commission (SEC)-governed law country wide Markets system and SEC suggestions, so the usage of an open source OS, with its perceived licensing and security hazards, may well be amazing. Rubinow is rarely worried, though.

    "there's always concern about open supply, however those issues are truly minor," Rubinow observed. "Up unless we have a bad adventure, it may be first-class. You really under no circumstances comprehend. Some situation may come out of the woodwork. … but we're regulated with the aid of the SEC. if they had any concerns with Linux operating systems, they'd have definitely voiced them."

    NYSE also uses a restrained quantity of virtualization in its fine assurance and checking out regimen, however it really is about it, Rubinow mentioned.

    "Virtualization is not free, and it uses up substances. It also has some latency that is not acceptable in trading. people note that tiny slowdown," Rubinow spoke of. "we now have only a handful of underutilized servers, so virtualization might shop us some funds and hardware, nonetheless it is rarely high up on our list."

    manhattan or bustAdding server capacity to NYSE's three East Coast records facilities has its challenges, not least of which is cost, with manhattan metropolis topping the list of essentially the most expensive areas to function an information middle in the U.S., according to Princeton, N.J.-primarily based site preference experts, the Boyd business Inc.

    apart from the three on the East Coast, NYSE has a different data center within the Midwest and two other "tiny" records centers in different parts of the nation. NYSE is on the hunt for an additional records middle web site to accommodate boom, also on the East Coast, Rubinow said.

    as a result of working statistics facilities in the japanese U.S. is expensive, Rubinow and his crew work with producers to ensure the hardware choices fit inside the limits of the records middle vigor availability. as an example, when densely packed, blade servers are wide-spread to generate extreme warmth, which may create cooling concerns. To evade this, Rubinow acquired warmth profile projections to determine what number of blades can also be packed into each and every rack and in which records middle to vicinity the servers.

    That pointed out, being close to Wall road, and the vast majority of NYSE valued clientele, is value the charge, he observed.

    "we're being as artistic as we can be with the space we've now, but we are trying to find a new space, which should be near our optimum customer enviornment," Rubinow noted. "Being close to our valued clientele is more crucial to us than discovering a cost-effective area to function. otherwise, we'd be following Google round."

    let us know what you consider in regards to the story; email Bridget Botelho, news creator.

    also, take a look at our information blog at

    Some well-known Kernel techniques | Real Questions and Pass4sure dumps

    This chapter is from the publication 

    The dialogue of operating gadget internals presents many challenges and opportunities to an writer. Our strategy is to discuss each enviornment of the kernel, agree with the challenges faced with the aid of kernel designers, and then explore the route taken towards the ultimate answer applied within the HP-UX code.

    earlier than we focus on HP-UX specifics, let's focus on some familiar challenges confronted via kernel designers. as with any programming project, there are generally a variety of how you can approach and resolve an issue. every so often the resolution is in keeping with the programmer's past adventure, and infrequently it's dictated with the aid of the certain necessities of each and every kernel design feature. As an working equipment matures, these particular person aspect options are often modified or "tweaked" with a purpose to tune a kernel's operating parameters and bring them into alignment with efficiency objectives or gadget benchmark metrics. The HP-UX working equipment is the manufactured from a continual growth manner that has enabled the refinement of core features and delivered many enhancements and services through the years.

    Kernel records constructions

    Programmers often use algorithms or borrow coding thoughts from a "bag-of-tricks" that belongs to the software construction community at massive. This regular competencies base consists of many points of particular activity to those that craft working gadget code. Let's discover one of the crucial challenges that kernel programmers face and take a look at to boost a fundamental realizing of just a few of the normal programmatic solutions they make use of.

    Static Lists (Static Tables)

    The kernel regularly must maintain an intensive listing of parameters concerning some records structure or managed useful resource. The simplest way to keep this classification of information is to create an ordered, static record of the attributes of each member of the record.

    each and every statistics constitution is defined according to the individual pieces of facts assigned to every element. as soon as every parameter is typed, the dimension (in bytes) of the constitution is common. These constructions are then kept in contiguous kernel house (as an array of structures) and can be simply listed for fast access.

    As a accepted commentary, and through no ability a set rule, the naming conference of those lists may additionally resemble here sample (see determine 3-3). If the name of the records structure for a single member of the list is defined as data_t, then the kernel pointer to the start of the checklist can be records*. The record could also be referenced with the aid of an array named statistics[x], and the number of facets would be kept in ndata. Many examples within the kernel comply with this conference, however by means of no capability all of them.

    03fig03.gifdetermine 3-3. Tables and Lists

    --> professionals

    The house necessary for a static listing ought to be allocated during equipment initialization and is often managed by using a kernel-tunable parameter, which is set prior to the building of the kernel graphic. the first entry in a static statistics table has the index cost of 0, which enables easy calculation of the starting tackle of each and every point inside the desk (assuming a fixed dimension for each member element).

  • instance

    anticipate that each and every data constitution carries exactly sixty four bytes of records and that the starting of the static record is defined through the kernel image mylist. in case you wanted to entry the facts for the list member with an index variety of 14, you might with ease take the tackle saved within the kernel pointer mylist* and add 14 × 64 to it to arrive at the byte tackle corresponding to the beginning of the 15th aspect in the list (remember that the record index begins with 0). If the structure is defined as an array, you could simplify the entry by way of referencing mylist[14] in your code.

  • Cons

    The main disadvantage to this strategy is that the kernel have to supply satisfactory checklist features for all talents scenarios that it may come upon. Many device administrators are regarded godlike, but very few are in reality clairvoyant! in the case of a static listing, the best means for it to grow is for the kernel to be rebuilt and the system rebooted.

    an additional consideration is that the aid being managed have to have an index quantity associated with it anyplace it has to be referenced within the kernel. whereas this may look essential at the start, believe in regards to the eventualities of initial task, index quantity reuse, resource sharing and locking, and the like.


    while this type of constitution is traditionally one of the vital commonplace, its lack of dynamic sizing and requirement to plan for the worst case has put it on the hit checklist for many kernel development tasks.

    Dynamic Linked Lists (Dynamic Tables)

    The individual facets of a list ought to be maintained in a way that makes it possible for the kernel to computer screen and control them. not like the aspects in a static checklist, the entire aspects of a dynamic list are not neatly grouped collectively in a contiguous reminiscence space. Their individual locations and relative order don't seem to be known or predictable to the kernel (as the identify "dynamic" suggests).

    it is a comparatively primary task so as to add features to an inventory as they're requested (featuring the kernel has an effective kernel reminiscence-administration algorithm, which is mentioned later). as soon as a knowledge constitution has been allocated, it ought to be linked with different buildings of the equal list. Linkage strategies fluctuate in complexity and comfort.

    as soon as a structure has been allocated and the correct information stored, the challenge is in getting access to the records in a timely manner. an easy index will not suffice due to the noncontiguous nature of the individual list facets. The option is to "walk" the list by way of following ahead pointers inserted into every listing point as a method of constructing a continuous path in the course of the record or to implement any other category of index information structure or hash characteristic. whereas a hash significantly reduces the access/search time, it is a calculated overhead and have to be used each time an item within the listing is needed.

    An further problem comes when it is time for the kernel to clear up a structure that isn't any longer essential. If the particular person aspects of the record were without problems linked by way of a single forward-linkage pointer, then the project of doing away with a single aspect from the checklist may also be time drinking. The listing point, which aspects to the aspect to be removed, ought to be identified as a way to repair the break in the chain that the removing will cause. These requirements result in the building of bidirectional linkage schemes, which enable for quicker deletion but require further overhead all over setup and protection.


    The leading enchantment to the dynamic record is that the supplies consumed through the listing are only allocated as they are necessary. If the need arises for extra checklist points, they are effectively allocated on the fly, and a kernel rebuild and reboot are not essential. additionally, when a listing factor is no longer mandatory, its space can be again to the kernel pool of purchasable reminiscence. This may reduce the universal measurement of the kernel, which may also positively affect performance on a equipment with tight memory dimension constraints.


    Nothing is free when it comes to programming code! The convenience of dynamic lists comes with a number of associated costs. The kernel should have an efficient technique to allocate and reclaim memory components of various sizes (distinct list structures have diverse aspect dimension necessities).

    The problem of the way to hyperlink individual checklist elements collectively increases the complexity and measurement of each facts constitution within the listing (more choices to be evaluated by the kernel designer!). The dynamic checklist creates further challenges within the realm of searching algorithms and indexing.


    The present flow is certainly towards a totally dynamic kernel, which necessitates incorporation of an ever-expanding quantity and variety of dynamic lists. The problem for the contemporary kernel dressmaker is to help ultimate the use and renovation of dynamic lists. there is abundant possibility here to consider outdoor the field and create wonderful options to the indexing and linkage challenges.

    resource Allocation

    An early challenge for a kernel dressmaker is to track the utilization of a system useful resource. The useful resource can be reminiscence, disk space, or attainable kernel information constructions themselves. Any merchandise that can be used and reused all the way through the operational life cycle of the equipment must to be tracked with the aid of the kernel.

    Bit Allocation Maps

    A bitmap is possibly one of the vital easiest means of conserving music of aid utilization. In a bitmap, each bit represents a set unit of the managed aid, and the state of the bit tracks its present availability.

    A aid need to be quantified as a set unit size, and the good judgment of the bitmap need to be described (does a 0 bit point out an obtainable useful resource or a used useful resource?). once these ground suggestions were decided, the map could be populated and maintained.

  • illustration

    In practices a useful resource bit map requires rather low renovation overhead. The precise size of the map will vary in line with the variety of useful resource contraptions being mapped. as the unit dimension of the resource raises, the map becomes proportionally smaller, and vice versa. The measurement of the map comes into play when it's being searched: the bigger the map, the longer the hunt can also take. Let's anticipate that we now have reserved a contiguous 32-KB block of kernel memory and we need to shop records there in 32-byte structures. It turns into a fairly simple problem to allocate a 1024-bit bitmap structure (128 bytes) to track our aid's utilization. if you deserve to find an attainable storage place, you operate a sequential search of the bitmap until you discover an accessible bit, set the bit to point out that the house is now used, and translate its relative place to point out the obtainable 32-byte enviornment within the reminiscence block.

  • pros

    The relative simplicity of the of the bitmap method makes it a pretty first-flow solution in many situations. A small map may well be used to tune a comparatively massive useful resource. Most processors feature meeting language–stage bit-look at various, bit-set, and bit-clear functions that facilitate the manipulation of bitmaps.


    because the measurement of the bitmap raises, the time spent locating an attainable aid also increases. If there is a necessity for sequential instruments from the mapped space, the allocation algorithms develop into a whole lot more complicated. A resource map is a programmatic settlement and isn't a resource lock via any skill. A renegade section of kernel code, which ignores the bitmapping protocol, may comfortably compromise the integrity of the bitmap and the resource it manages.


    If a device useful resource is of a static dimension and all the time utilized as a set-sized unit, then a bitmap might also show to be the most least expensive administration method.

    resource Maps

    an extra classification of fastened aid mapping involves the utilization of a structure called a aid map (see determine 3-four). right here is a normal explanation of the strategy as there are lots of differing purposes of this technique. within the case of a resource map, you have got a useful resource of a hard and fast size against which particular person allocations of varying sizes need to be made.

  • illustration

    For our instance, let's consider a simple message board. The message board has 20 attainable lines for message screen; each and every line has room for 20 characters. the full resource has room for 400 characters, however particular person messages must be displayed on sequential traces. trust posting both following messages:

  • 03fig04.gifdetermine 3-4. aid Maps

    To prevent this sort of condition, a aid map can be employed to allocate sequential lines. each and every entry within the useful resource map would element to the subsequent block of accessible line(s) on the board.

  • If the message board have been blank, then there could be just one entry in our resource map pointing to the primary line and pointing out that 20 strains have been sequentially obtainable. To record the primary message, we'd allocate the primary three traces from the board, regulate our resource map entry to aspect to the fourth line, and modify the count number to 17. to add the 2nd message to the board, we would allocate two more lines and adjust the first entry within the map to point to the sixth line, with the count number adjusted to 15.

  • In effect a resource map facets to the unused "holes" within the aid. The size of the useful resource block tracked by using each and every map entry varies in response to usage patterns.


    A resource map requires fairly few precise entries to manage a large variety of elements. If the allocation block measurement varies and needs to be contiguously assigned, then this could be your greatest guess.


    Map entries are consistently being inserted and deleted from the maps. This requires steady moving of the particular person map entries (the saving grace right here is that there are tremendously few entries). a different difficulty is the dimension of the resource map itself: in case you run out of entries, then freed components might also no longer be accounted for and in impact might be misplaced (a kind of memory leak) to gadget usage except a reboot.


    aid maps have lengthy been utilized through gadget V Interprocess communique kernel features, and if care is taken of their sizing, they're very efficient.

    browsing Lists and Arrays

    where there are arrays and lists of information buildings, there is always a need to search for selected aspects. in lots of situations, one records structure may have an easy pointer to linked constructions, however there are times when all you comprehend is an attribute or attributes of a favored constitution and not an exact handle.

    Hashtables: an alternative to Linear Searches

    searching a long record merchandise via merchandise (regularly known as a sequential or linear search) can be very time drinking. To in the reduction of the latency of such searches, hash lists are created. Hashes are a kind of indexing and can be used with either static arrays or linked lists to speed up the place of a selected factor within the list.

    to use a hash, a widespread attribute of the merchandise being looked for is used to calculate an offset into the hashtable (hash arrays are commonly sized to a power of two to help within the calculation and truncation of the hashed price to in shape the array size). The hashtable will include a pointer to a member of the listing that suits the hashed attribute. This entry may additionally or may no longer be the specific entry you are searching for. whether it is the item you are looking for, then your search is over; if now not, then there can be a forward hash-chain pointer to a further member of the list that shares the identical hash attribute (if one exists). during this manner, you will ought to follow the hash-chain pointers unless you discover the relevant entry. when you will nonetheless need to operate a search of one or greater linked objects, the size of your search might be abbreviated.

    The efficiency depends on how evenly dispensed the attribute used for the hash algorithm is inside the members of the list. another key element is the usual dimension of the hashtable.

  • example

    consider you have got a listing of your pals' names and call numbers. As you add names and numbers to the list, they are with no trouble placed in an attainable storage slot and not saved in any selected order. historically, you could type the list alphabetically each time an entry is made, but this is able to require "reordering the deck." consider instead the use of a hashtable.

    As every entry is made, the number of letters in each name is counted; if there are greater than 9, then best the ultimate digit of the count number is kept. A separate hashtable array with 10 entries is also maintained with a pointer to a reputation in the listing with that hash count number. As each and every name is delivered to the list, it's linked to the entire different listing contributors with the same hash count number. See determine three-5.

    03fig05.giffigure three-5. Hashtables and Chains

  • in case your record had a hundred names in it and your have been hunting for Fred Flintstone, the device would first complete the persona count number (Fred has four and Flintstone has 10, a complete of 15 counting the space between the names), which might ship us to hash[5]. This entry would point to a name whose hash count number is 5; if this were now not the Fred Flintstone entry, you could comfortably follow the embedded hash-chain pointer unless you found Fred's entry (or reached the end of the list and failed the search).

    If there have been 100 entries in the table and 10 entries in the hashtable, the usage of a standard distribution, then every hash chain would have 10 entries. On common, you would have to follow someone chain for half of its size to get the information you desired. that could be a 5-linkage pointer search in our illustration. If we needed to perform a sequential search on the unordered records, the ordinary search size would were 50 aspects! Even given that the time required to perform the hash calculation, this could result in appreciable rate reductions.

    whereas this illustration is enormously simplified, it does show the fundamentals of hash-headers and hash chains to velocity up the vicinity of the "correct" statistics structure in a randomly allocated facts desk.


    Hashing algorithms offer a versatile indexing system that isn't tied to fundamentals comparable to numerical sequence or alphabetic order. significant attributes are used to calculate an offset into the hash-chain header array. The header elements to a linked record of all objects sharing the identical hash attribute, accordingly decreasing the standard search time required to find a particular item in the list.


    The selected attributes used for the hash could be just a little abstract in theory and should be carefully considered to assure that they aren't artificially influenced and don't result in uneven distributions to the particular person chains. If the measurement of the resource pool being hashed grows, the length of the particular person chains may additionally turn into excessively lengthy and the payback may be diminished.

    while the simple thought of hashing is awfully primary, each and every implementation is in response to selected attributes, some numeric, some persona-primarily based, and so forth. This requires the programmer to cautiously study the facts sets and determine which attribute to make use of as a key for the hash. generally, essentially the most obvious one may additionally no longer be the greatest one.


    Hashing is right here to live (at the least for the foreseeable future). Make your peace with the concept, as you'll see various implementations throughout all areas of kernel code.

    Binary Searches

    When it involves shopping a hard and fast checklist for a price, there are many approaches. The brute-drive system is to effortlessly birth with the primary point and proceed in a linear manner in the course of the entire checklist. In idea, if there have been 1024 entries within the list, the standard search time can be 512 tests (from time to time the item you are trying to find would be at the entrance of the checklist and often towards the end, so the general would be 1024/2 or 512).

    yet another method comprises the use of a binary search algorithm. The resolution branch employed by the algorithm is in line with a binary-conditional test: the merchandise being proven is both too excessive or too low. in order for a binary search to work, the records within the list have to be ordered in an increasing or decreasing order. If the records is randomly disbursed, an additional type of search algorithm may still be used.

    consider a 1024-aspect checklist. we'd birth the search by means of testing the aspect within the core of the listing (factor 512). counting on the outcome of this check, we might then verify both point 256 or 768. we'd keep halving the last listing index offset except we discovered the favored element.


    Following this formula, the worst-case search length for our theoretical 1024-factor listing could be 10! evaluate this to 1024 for the brute-force linear search formula.


    while the discount in the variety of individual comparisons is impressive, the simple list features must be ordered. The have an effect on of this on list upkeep (including items to or getting rid of them from the list) may still no longer be underestimated. An unordered list may be easily managed by utilizing a simple free-record pointer and an embedded linkage pointer between all of the unused facets of a listing. If the record is ordered, then lots of its individuals could need to be moved each time an item is brought or faraway from the list.


    we have regarded simplest a extremely primary variety of binary search. Kernels employ many diversifications on this theme, every tuned to suit the wants of a particular structure.

    Partitioned Tables

    contemporary architectures current kernel designers with many challenges; one is the mapping of elements (both contiguous and noncontiguous). consider the assignment of tracking the web page-frames of actual memory on a system. If physical memory is contiguous, then a simple usage map could be created, one entry per pageframe, the web page number may be the identical as the index into the array.

    On up to date phone-oriented systems, there can be numerous memory controllers on separate busses. frequently, the hardware design dictates that every bus be assigned a element of the reminiscence tackle house. This type of tackle allocation may end up in "holes" in the actual memory map. using partitioned tables presents a method to successfully map round these holes.

  • illustration

    consider the greatly simplified example in determine three-6. in order to control a useful resource of sixteen, gadgets we could use an easy 16-element array (as shown on the left side of the determine). during this example, there is a hole in the resource allotment; physically, the fifth through 14th elements are missing. If we use the fundamental array formula, sixteen aspects will still be necessary in the array if we are looking to retain the relationship between the array index and the corresponding tackle of the useful resource.

    03fig06.giffigure three-6. Partitioned Tables

    by means of switching to a two-tier partitioned desk, we will map the components on each side of the hole and cut back the quantity of table house vital. the primary tier is an easy array of 4 aspects, each both a sound pointer to a block of facts constructions or a null pointer signifying that the associated block of substances does not exist.

    in addition to the pointer, an offset cost is stored in each and every aspect. here's used in the case the place the hole extends in part right into a block's range (as does the remaining pointer in our illustration). The offset permits us to skip to the element containing the primary valid information constitution.

    Let's compare the effort required to find a data constitution. in case you crucial the guidance involving the 15th aid and were the use of the simple array method, you possibly can most effective ought to index into the 15th point of the array (records[14]).

    If the partitioned strategy had been getting used, you could first divide the element tackle by the dimension of the second-tier buildings. For our illustration that could be 14/four, which would yield three with a the rest of 2. you may then index into the first-tier array to the fourth element (index = three), observe the pointer discovered there, and use the remainder to offset into the partitioned table to the third factor (index = 2).

  • In our simplified instance, the single array approach required room for 16 information structures however there were most effective six resources being mapped. The partitioned approach required room for less than eight data constructions (in two partitioned tables of four elements every) plus the very standard 4-aspect first-tier structure.

    at the start glance, it could now not look that the payback is value the additional effort of navigating two tables, but here is a really standard example. As we mentioned earlier, the strategy is used to control tables tremendous enough to map all of the physical web page-frames of a latest commercial enterprise server! There will also be hundreds of thousands of competencies pages wanting their personal information structures (and large holes can also exist). we can see partition tables in use when we discuss reminiscence management.


    The cost of partitioned tables is within the discount of kernel reminiscence utilization. The less reminiscence used with the aid of the kernel, the more purchasable for consumer classes!


    The components definitely has only a few drawbacks; the referencing of a map element is now a two-step technique. The map element quantity ought to be divided through the number of points in each and every partitioned table constitution (2d-tier structure) to yield an index into the first-tier structure. The the rest from this operation is the offset into the second-tier constitution for the favored aspect. In observe, the partitioned tables are often sized to an influence of two, which reduces the calculation of the offsets to fundamental bit-moving operations.


    Partitioned tables are dictated by way of the architecture and are a essential tool within the kernel fashion designer's bag of tricks.

    The B-Tree Algorithm

    The b-tree is a a bit advanced binary search mechanism that includes making a collection of index buildings arranged in a sort of relational tree. each and every structure is known as bnode; the number of bnodes depends on the variety of aspects being managed. the primary bnode is pointed to through a broot structure, which defines the width and depth of the overall tree.

    probably the most interesting and powerful features of the b-tree is that it may be accelerated on the fly to accommodate a transformation within the variety of objects being managed. B-timber can be used to map a small number of objects or hundreds of hundreds by way of easily adjusting the depth of the structure.

    The essential bnode consists of an array of key-price pairs. the key statistics have to be ordered in an ascending or descending method. To locate a obligatory value, a linear search is performed on the keys. This may also seem to be an old school strategy, however let's believe what happens as the records set grows.

    the primary situation is the size of the bnode. A b-tree is said to be of a particular order. The order is the variety of keys in the array constitution (minus 1—we are able to clarify this as we talk about a simple instance). If we now have a third-order b-tree, then at most we might have three keys to determine for each search. Of direction, we may best reference three values with this basic constitution!

    with a purpose to develop the scope of our b-tree's usefulness, we have to grow the depth of the tree. once a b-tree expands past its order, further bnodes are created and the depth of the tree is elevated.

    handiest bnodes on the lowest level of the tree include key-price facts. The bnodes in any respect different ranges include key-pointer data. This skill that with the intention to locate a selected price, we should habits a search of a bnode at each and every level of the tree. every search, on normal, requires half as many examine operations as there are keys within the bnode (the order). This capacity that the commonplace search length is defined as (order/2) × depth. Optimization is done with the aid of adjusting each the order and the depth of the b-tree.

  • instance: turning out to be the b-tree

    From determine 3-7, consider a really simple illustration of a 3rd-order b-tree. The fashioned bnode has keys: 1, 2, 3. every thing fits in a single bnode, so the depth is easily 1.

    03fig07.giffigure 3-7. B-bushes

    when we add a fourth key, 4, to the tree, it fills the bnode to capability and factors the increase of the tree. If the variety of keys in a bnode exceeds the order, then it is time to break up the node and grow the tree.

    To grow this primary tree, we create two new bnode structures and movement half of the current key–price pairs to each and every. be aware that the information is packed into the first two entries of every of the brand new bnodes, which allows for for room to grow.

    subsequent, we must alter the depth price in the broot facts structure that defines the tree. The normal bnode have to also be reconfigured. First, it is cleared, and a single key's created.

    Let's take a closer seem to be at the bnode constitution. note that there are truly extra price slots than there are key slots. This allows for two tips that could be created on the subject of every key entry. The pointer down and to the left is used in case you are seeking for a key of a lower price. The pointer down and to the appropriate is used in case you are trying to find one it truly is superior than or equal to the important thing.

    Let's try locating a value given a key = 2:

    search for a key = 2. as a result of there is not any perfect in shape, we seek a key that is > 2 and follow the pointer down and to the left of that key to the subsequent bnode.

    search for a key = 2. A match here will yield the appropriate price. We know that here is a worth and never another pointer, when you consider that the broot structure instructed us we had a depth of two!

  • observe that the key values do not need to be sequential and can be sparse so long as they're ordered. Searches on the bottom level of the tree return both a worth or a "no fit" message.

    The seek a key all the time makes an attempt to find a perfect in shape yielding either a price or a pointer to the next lower stage. If no fit is found and we aren't on the lowest level, right here good judgment is used. in case your search key lays between two adjoining key entries, the pointer to the next degree lies under and between them. A search key less than the primary key entry uses the first pointer in the bnode. in case your search key's larger than the closing valid key in the bnode, then the ultimate valid pointer is used.


    B-bushes could be grown dynamically, whereas their desk upkeep is inconspicuous. This makes them most useful for managing kernel structures that modify in dimension. Key values can be packed or sparse and delivered to the table at any time, proposing for a flexible scope.


    an additional benefit is that given a sufficiently sized order, a b-tree may also develop to manage a large variety of objects while preserving a fairly constant search time. agree with a 15th-order b-tree: the primary depth would map 16 items, the 2nd depth would map 256 items, and the third depth would yield a scope of 4096 whereas simplest requiring the quest of three bnodes! This class of exponential boom makes it very time-honored for administration of small to huge components.

    The b-tree, binary-tree, and balanced-tree belong to a family unit of connected search structures. while the b-tree has a modest renovation overhead due to its primary correct-down pointer logic, its growth algorithm can result in carefully populated bnodes. This increases the number of nodes required to map a given number of facts values. As with most techniques, we change table measurement for maintenance cost.

    an extra concern is that whereas the b-tree can also develop its depth to sustain with demand, it could not exchange its order (with out in reality reducing it all the way down to the ground and rebuilding it from scratch). This capability that designers deserve to pay attention to its knowledge usage when sizing the order in their implementations.


    The b-tree requires slightly of study prior to its implementation but offers a very good system for the mapping of ordered dynamic lists ranging in dimension from moderate to huge. we are able to see a pragmatic software of the b-tree once we assess kernel management of virtual reminiscence area buildings.

    Sparse Tables

    We mentioned using a hash to speed entry to contributors of a static, unordered array. What would ensue if the hash measurement were aggressively expanded (even to the dimension of the array it referenced or higher)? originally you may consider this would be a fine answer: quite simply create a hashing algorithm with enough scope, and lookups turn into a single-step system. The problem is that the kernel information array and its corresponding hash might become prohibitively gigantic as a way to guarantee a unique reference.

    A compromise is to dimension the information structure huge adequate to grasp your worst-case element count number and hope that the hashing algorithm is completely distributive in its nature. In an excellent situation, no two active points would share the same hash.

    in the much less-than-most useful real world, there may be situations the place two records aspects do share a common hash. We might also clear up the issue by dynamically allocating an additional facts structure backyard the fastened array and creating a ahead hash-chain hyperlink to it.

    always, this step is not critical if the hash method is sufficiently distributive. In apply, a forward pointer can also most effective be mandatory in a very small percentage of the situations (lower than 1% or 2%). within the very rare case where a third factor must share the same hash, an further structure could be chained to the 2d, one and so on (reference figure three-eight).

    03fig08.giffigure 3-eight. Sparse Tables


    Sparse lists vastly in the reduction of the average search time to find items in unordered tables or lists.


    Sparse lists require the kernel to manipulate the purchasable sparse records-point areas as yet another kernel useful resource. As there's a possibility that the information point first pointed to may additionally now not be the genuine one you are seeking for, the goal structure need to include ample statistics to validate that it's or isn't the one you desire. If it is rarely, a pursuits must be developed to "walk the chain."


    Spare lists work ideal when there is some familiar attribute(s) of the desired facts set that could be used to generate a sufficiently tremendous and distributive hash cost. the chances of needing to create a forward chain pointer reduce significantly as the scope of the hash increases. we can see an illustration of this approach within the HP-UX kernel's virtual-to-physical web page-frame mapping. In exact use, it is a one-in-a-million opportunity to find a hash-chain with greater than three linked facets!

    The bypass record

    on the earth of search algorithms, the skip listing is a new youngster on the block. Its use became first outlined in the 1990s in a paper prepared for the Communications of the association for Computing equipment (CACM) by way of William Pugh of the institution of Maryland. For additional info, discuss with

    The algorithm could be employed to cut back search instances for dynamic linked lists. The individual listing features need to be assigned to the record in keeping with some ordered attribute. This method works neatly for linked lists with simplest a dozen or so members and equally as smartly for lists of several hundred participants.

    at the start look, bypass lists seem like without problems a collection of ahead- and reverse-linkage pointers. Upon closer examination, we see that some aspect directly to a neighbor, while others pass a couple of in-between structures. The magnificent part is that the number of aspects skipped is the influence of random assignment of the pointer structures to each and every record member as it is linked into the listing.

    listing protection is relatively simple. so as to add a brand new member point, we easily skip during the record until we discover its neighboring members. We then with no trouble link the brand new structure between them. The removing of a member follows the same common sense in reverse.

    When a new member is introduced, we must make a decision at which tiers it should be linked. The implementation used within the HP-UX pregion lists uses a pass pointer array with 4 aspects. All members have a primary-stage ahead pointer. the percentages are one in four that it's going to have a second-level pointer, one in four of these may have a 3rd-level pointer, and one in four of these may have a fourth-level pointer. As features may well be introduced or removed from the list at any time, the genuine distribution of the pointers takes on a pseudorandom nature.

    To facilitate the components, a symbolic first point is created, which all the time consists of a ahead pointer at each of the bypass degrees. It also shops a pointer to the optimum lively degree for the record. See determine three-9.

  • illustration

    From determine 3-9, let's expect that we need to find the structure with the attribute 9678. within the checklist nexus structure, we see that the maximum stage lively pointer is at subsequent[2], so we comply with it. This structure has an attribute cost of 5255, so we deserve to proceed our search at this stage.

    We arrive lower back on the starting aspect structure, so we go into reverse to the 5255 constitution, drop down a stage to next[1], and proceed.

    We now arrive at the constitution with the 9678 attribute—it be a suit! Our search is over.

    in the instance, it took handiest three searches. a simple binary search would have taken four searches.

  • 03fig09.gifdetermine three-9. pass list


    The pass listing offers an interesting approach for looking that often consequences in a reduction of search times when in comparison to an easy binary method. adding and eliminating participants to and from the listing within reason short.


    It requires the creation of a multielement array for the forward linkages. The random nature of the pointer task doesn't take into account the relative measurement or frequency of use of the a variety of record points. a frequently referenced constitution should be would becould very well be inefficiently mapped by way of the success-of-the-draw (in our illustration we beat the binary formula, but different contributors of our list would not: are attempting attempting to find the 5015 constitution).


    regardless of the random nature of this beast, the universal impact may well be a net-sum benefit if the ratio between the variety of items and the number of ranges is cautiously tuned.

    Operations Arrays

    contemporary kernels are often required to adapt to quite a lot of different subsystems that may give competing or alternate processes to the identical management project. A case in element is that of a kernel that must assist numerous file gadget implementations at the identical time.

    to achieve this intention, certain file systems can be represented within the kernel by means of a virtual object. digital representation masks all references to the genuine object. here is all smartly and first rate, however what if kernel routines mandatory to interact with the precise object required code and assisting records elegant upon category-specific attributes? An operations array, or vectored jump table, could be of provider here.

  • example

    agree with figure three-10. right here we see a simple kernel table with 4 aspects, each and every representing a member of a digital record. each listing member has its actual v_type registered, a sort-specific v_data[] array, and a pointer to a v_ops[] operational array.

    03fig10.gifdetermine 3-10. Operations Arrays: A Vectored start table

    For this model to work, the variety of entries in the operational array and the services they point to must be matched for every type the kernel is expected to tackle. In our example, there are four operational target functions: open(), shut(), examine(), and write(). at the moment, our equipment has only two adaptations labeled classification: X and Y.

    When a events is known as through a vectored bounce referenced through v_ops[x], it's passed the handle of the virtual objects v_data[] array. This allows for the final class-specific function to work with a knowledge set category that it is familiar with.

    The fruits is that each one different kernel objects want handiest to request a call to v_ops[0] to instigate an open() of the digital object devoid of challenge or abilities of no matter if it is of type X or Y. The operations array will deal with the redirection of the call. In observe, we will see many examples of this category of structure within the kernel.

  • pros

    The can charge of redirecting a system call via a vector leap table is awfully low and for probably the most half transparent to all that use it.


    In debugging, here's yet one other stage of indirection to take care of.


    The vectored leap table, or operational array, gives a very positive abstraction layer between class-selected, kernel-resident capabilities, and different kernel subsystems.

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    Intel’s SGX blown wide open by, you guessed it, a speculative execution attack | real questions and Pass4sure dumps

    reader comments 138 Share this story
  • Foreshadow explained in a video.

    Another day, another speculative execution-based attack. Data protected by Intel's SGX—data that's meant to be protected even from a malicious or hacked kernel—can be read by an attacker thanks to leaks enabled by speculative execution.

    Further Reading “Meltdown” and “Spectre”: Every modern processor has unfixable security flaws

    Since publication of the Spectre and Meltdown attacks in January this year, security researchers have been taking a close look at speculative execution and the implications it has for security. All high-speed processors today perform speculative execution: they assume certain things (a register will contain a particular value, a branch will go a particular way) and perform calculations on the basis of those assumptions. It's an important design feature of these chips that's essential to their performance, and it has been for 20 years.

    But Meltdown and Spectre showed that speculative execution has security implications. Meltdown (on most Intel and some ARM processors) allows user applications to read the contents of kernel memory. Spectre (on most Intel, AMD, and ARM chips) can be used to attack software sandboxes used for JavaScript in browsers and, under the right conditions, can allow kernel memory or hypervisor memory to be read. In the months since they were first publicized, we've seen new variants: speculative store bypass, speculative buffer overflows, and even a remotely exploitable version of Spectre.

    What's in store today? A new Meltdown-inspired attack on Intel's SGX, given the name Foreshadow by the researchers who found it. Two groups of researchers found the vulnerability independently: a team from KU Leuven in Belgium reported it to Intel in early January—just before Meltdown and Spectre went public—and a second team from the University of Michigan, University of Adelaide, and Technion reported it three weeks later.

    SGX, standing for Software Guard eXtensions, is a new feature that Intel introduced with its Skylake processors that enables the creation of Trusted Execution Environments (TEEs). TEEs are secure environments where both the code and the data the code works with are protected to ensure their confidentiality (nothing else on the system can spy on them) and integrity (any tampering with the code or data can be detected). SGX is used to create what are called enclaves: secure blocks of memory containing code and data. The contents of an enclave are transparently encrypted every time they're written to RAM and decrypted on being read. The processor governs access to the enclave memory: any attempt to access the enclave's memory from outside the enclave should be blocked.

    The value that SGX offers is that it allows these secure environments to be created without having to trust the integrity of the operating system, hypervisor, or any other layers of the system. The processor itself validates and protects the enclave, so as long as the processor is trusted, the enclave can be trusted. This is attractive in, for example, cloud-hosting scenarios: while most people trust that the cloud host isn't malicious and isn't spying on sensitive data used on its systems, SGX removes the need to assume. Even if the hypervisor and operating system are compromised, the integrity and confidentiality of the enclave should be unaffected.

    And that's where Foreshadow comes into play.

    Foreshadow was, er, foreshadowed

    All of these speculative execution attacks follow a common set of principles. Each processor has an architectural behavior (the documented behavior that describes how the instructions work and that programmers depend on to write their programs) and a microarchitectural behavior (the way an actual implementation of the architecture behaves). These can diverge in subtle ways. For example, architecturally, a program that performs a conditional branch (that is: comparing the contents of two registers and using that comparison to determine which piece of code to execute next) will wait until the condition is known before making the branch. Microarchitecturally, however, the processor might try to speculatively guess at the result of the comparison so that it can perform the branch and continue executing instructions without having to wait.

    If the processor guesses wrong, it will roll back the extra work it did and take the correct branch. The architecturally defined behavior is thus preserved. But that faulty guess will disturb other parts of the processor—in particular, the contents of the cache. The guessed-at branch can cause data to be loaded into the cache, for example (or, conversely, it can push other data out of the cache). These microarchitectural disturbances can be detected and measured—loading data from memory is quicker if it's already in the cache. This allows a malicious program to make inferences about the values stored in memory.

    The closest precursor to the new Foreshadow attack is Meltdown. With Meltdown, an attacker would try to read kernel memory from a user program. The processor prohibits this—the permissions for kernel memory don't allow it to be read from user programs—but the prohibition isn't instant. Execution continues speculatively for a few instructions past the illegal read, and the contents of cache can be modified by that execution. When the processor notices that the read was illegal, it generates an exception and rolls back the speculated execution. But the modifications to cache can be detected, and this can be used to infer the contents of kernel memory.

    For Foreshadow, the data of interest is the encrypted data in the enclave. The overall pattern is the same—attempt to read enclave memory from outside the enclave, allow speculative execution to modify the cache based on that data that was read, and then have the processor abort the speculation when it realizes that it's protected-enclave memory and that reading it isn't allowed. The attack depends on the fact that only data in main memory is encrypted: once it's inside the processor in a cache, it's decrypted. Specifically, if the data is in level 1 cache, the speculative execution can use it before the processor determines that there's no permission to use it.

    More complicated than Meltdown

    The details of the Foreshadow attack are a little more complicated than those of Meltdown. In Meltdown, the attempt to perform an illegal read of kernel memory triggers the page fault mechanism (by which the processor and operating system cooperate to determine which bit of physical memory a memory access corresponds to, or they crash the program if there's no such mapping). Attempts to read SGX data from outside an enclave receive special handling by the processor: reads always return a specific value (-1), and writes are ignored completely. The special handling is called "abort page semantics" and should be enough to prevent speculative reads from being able to learn anything.

    However, the Foreshadow researchers found a way to bypass the abort page semantics. The data structures used to control the mapping of virtual-memory addresses to physical addresses include a flag to say whether a piece of memory is present (loaded into RAM somewhere) or not. If memory is marked as not being present at all, the processor stops performing any further permissions checks and immediately triggers the page fault mechanism: this means that the abort page mechanics aren't used. It turns out that applications can mark memory, including enclave memory, as not being present by removing all permissions (read, write, execute) from that memory.

    Additional techniques were also devised to reduce the chance of data in level 1 cache being overwritten during the attack and increase the amount of information that can be read. With a malicious kernel driver, the full contents of the enclave can be read. Normally "with a kernel driver" isn't an interesting attack vector—kernel code is meant to be able to do more or less anything anyway—but SGX is explicitly meant to protect secrets even in the face of a hostile, compromised kernel.

    As such, data that should be secret and encrypted and visible only to trusted SGX code can be read by an attacker. Moreover, by using Foreshadow to read data from special Intel-provided enclaves, an attacker can fraudulently create their own enclaves with compromised integrity. There are also additional risks if multiple enclaves are running simultaneously in different hyperthreads on the same physical core; one enclave can attack the other.

    The researchers stress that their work doesn't undermine the basic design of SGX; Foreshadow is a quirk of the way speculative execution interacts with SGX, and, with that quirk resolved, the security of the system is restored (though historic encrypted data could potentially have been tampered with).

    When the attack was reported to Intel, the company performed its own investigation. It discovered that SGX data isn't the only thing that's at risk. The processor also has other specially protected zones of memory: the Extended Page Tables used by hypervisors, and memory used by System Management Mode (SMM), which can be used for power management or other low-level functions. As with the SGX data, the EPT and SMM data that's held in level 1 cache can be speculatively read and, hence, leaked to an attacker if memory is marked as being not present.

    Normally, access to EPT memory undergoes additional translation into a physical address, and access to SMM memory has a special permissions check to ensure the processor is in management mode. But when memory is marked as not present, the permissions-checking terminates early, bypassing this special handling.

    Intel has thus dubbed the flaw the "Level 1 Terminal Fault" (L1TF): data in level 1 cache can be leaked because the permissions check terminates too soon.

    The good news? Big parts are fixed already

    As with many of the other speculative execution issues, a large part of the fix comes in the form of microcode updates, and in this case, the microcode updates are already released and in the wild and have been for some weeks. With the updated microcode, every time the processor leaves execution of an enclave, it also flushes the level 1 cache. With no data in level 1 cache, there's no scope for the L1TF to take effect. Similarly, with the new microcode leaving management mode flushes the level 1 cache, protecting SMM data.

    The microcode also gives operating systems the ability to completely flush the level 1 data cache (without altering any other cache). Hypervisors can insert these flushes at certain points to protect the EPT data. Operating systems should also be updated to ensure that their mapping from virtual addresses to physical addresses follows certain rules so that secret data can never find itself in level 1 cache inadvertently.

    These cases don't, however, completely eliminate the risks, especially when hyperthreading is used. With hyperthreading, one logical core can be within SGX, hypervisor, or SMM code, while the other logical core is not. The other logical core can thus snoop on level 1 cache, and the extra cache flushes can't prevent this (though they can certainly make it less convenient, due to the increased chance of a flush occurring during an attack).

    This concern is particularly acute with virtual machines: if two virtual machines share a physical core, then the virtual machine using one logical core can potentially spy on the virtual machine using the other logical core. One option here is to disable hyperthreading on virtual-machine hosts. The other alternative is to ensure that virtual machines are bound to physical cores such that they don't share.

    For SGX data, however, the L1TF risk with hyperthreading enabled can't be completely eliminated.

    Longer term, Intel promises to fix the issue in hardware. Cascade Lake processors, due to ship later this year, will not suffer the L1TF (or Meltdown) issues at all, suggesting that the new processors will change how they handle the permission checks to prevent speculative execution from running ahead of permissions checks.

    Listing image by Conor Lawless / Flickr

    Intel Hardware Level Speculative Execution To Blame For Kernel Bug – KPTI Workaround Introduces Performance Hits Up To 23% On Average | real questions and Pass4sure dumps

    It has been a little over 48 hours since the Intel kernel bug was first reported and while we don’t have an official comment from Intel yet, it looks like there are some additional details of what the actual problem is. Those in the know are allegedly under embargo but courtesy of AMD’s statement on what ‘isn’t’ wrong with their x86 processors, we have a fairly good idea of what the bug entails. The repercussions of this could have severe consequences for Intel’s standing as a company and as a supplier of x86 microprocessors – particularly in the enterprise ecosystem.

    AMD spills the beans: Hardware level speculative execution to blame for the Intel Kernel bug; cannot be patched using a microcode update and will require OS level KPTI to patch

    Before we get into any other details, a background on the problem. The bug was discovered at a hardware level and pertains to an exploit that is capable of granting kernel level access to malicious parties. Since this exists at the hardware level, a patch via microcode is apparently not possible. The only known workaround is via the OS, which would require an OS re-design which Windows is working on and Linux has already rolled out.

    Word on the street is that Microsoft is scrambling to get this patched come Tuesday and the changes were already seeded to beta testers running insider builds. Here’s the catch though, any patch could introduce a crucial time penalty to the system which basically means that in some instances the CPUs could drastically slow down. We have seen numbers quoted of up to 30%, but the conservative estimates point to a roughly 17% slowdown. So what exactly is the problem?

    Well, before we get into that, here is the statement from AMD, which basically spilled the beans on what the issue is:

    AMD processors are not subject to the types of attacks that the kernel page table isolation feature protects against. The AMD microarchitecture does not allow memory references, including speculative references, that access higher privileged data when running in a lesser privileged mode when that access would result in a page fault.

    Since Intel has been very tight lipped about this issue, we can deduce fairly easily from this statement that the problem has to do with speculative references in Intel’s processors, which AMD CPUs don’t have. Speculative execution is basically a form of pre-emption which tries to predict what code is going to be run, and then fetch it and execute it before the actual order comes through and keeping pipelines ready. The point of this is to have the kernel absolutely ready for any command, instead of letting it wait around.

    The problem, as it is clear from AMD’s comments, is that you can exploit this feature to speculatively execute code that would normally be blocked as long as you stop the actual code from running before a check can be performed. What this essentially means is that a ring-3-level user can read ring-0-level kernel data by using speculative execution since the privilege check won’t actually be performed till the code is executed on the main.

    The kernel layer is currently present in all processes’ virtual memory address space to ensure a fast handover during code execution but is completely invisible to all programs. The kernel will basically try to predict what code will be executed next and when a program makes a system call to the kernel, it will already be ready and primed for the handover. This can significantly increase execution times but as it is clear now, also represents a very troublesome security flaw since no privilege check is present at the kernel stage.

    The only way to get around this hardware level feature is to use what is called a Kernel Page Table Isolation (KPTI) technique which will make the kernel completely blind to the system and remove it from the virtual memory space until a system call occurs. Basically, where it was an invisible stage hand hidden just behind the curtain, now it won’t be on the stage at all until it’s called. Needless to say, this could introduce severe time penalties in context-switching heavy situations where a lot of system calls are required.  The Linux team also mulled over FUCKWIT (Forcefully Unmap Complete Kernel with Interrupt Trampolines) which should give you an idea of how frustrating the bug is for developers.

    According to some sources, this number can range anywhere from 5% to 30% depending on which type of processor you have since modern CPUs have a feature called PCID which can reduce the performance hit. According to an existing KPTI workaround posted at Postgresql, you should expect a 17% best case slowdown and a worst case 23% slowdown. In any case, all sources agree that a slowdown will almost definitely occur and this is not something Intel can simply patch with a microcode update. AMD processors at this time are unaffected since they do not utilize speculative execution.

    So the obvious next question becomes who will this impact and how will this impact end users. Well, the good news is, if you are reading this article you are probably a gamer or a PC tech enthusiast and you will see almost no difference once the patch is applied (gaming and basic rendering are not context-switching heavy payloads). Enterprise clients like Google EC2 and Amazon Compute Engine however, will be drastically affected since they use VMs which this can severely compromise. Secondly, as a general user, your passwords and other sensitive information may be stored in the kernel memory and this bug could be used to access that information (Update: Working proof of concept of password being pulled from kernel mem leak over here).

    Windows is expected to roll out a patch come Tuesday and Apple should also follow up soon. All that remains is an official response from the company itself.

    Update: First benchmarks with KPTI work around from Phoronix showing performance degradation (1% to 53% depending on use case), gaming not affected

    The folks over at Phoronix did some preliminary synthetic testing and were able to observe performance degradation that ranges from 19% to a massive 53% depending on the exact situation and benchmark tested. Scenarios that should show no effect are showing less than a 1% deviation from the initial benchmark. We expect other publications to do their own benchmarks as well once Intel responds.

    Update: Intel’s official response

    Intel has rolled out their official response on this and assured that the bug won’t affect the average user (as we have already stated) and that they are actively working with other companies to resolve this:

    Intel and other technology companies have been made aware of new security research describing software analysis methods that, when used for malicious purposes, have the potential to improperly gather sensitive data from computing devices that are operating as designed. Intel believes these exploits do not have the potential to corrupt, modify or delete data.

    Recent reports that these exploits are caused by a “bug” or a “flaw” and are unique to Intel products are incorrect. Based on the analysis to date, many types of computing devices — with many different vendors’ processors and operating systems — are susceptible to these exploits.

    Intel is committed to product and customer security and is working closely with many other technology companies, including AMD, ARM Holdings and several operating system vendors, to develop an industry-wide approach to resolve this issue promptly and constructively. Intel has begun providing software and firmware updates to mitigate these exploits. Contrary to some reports, any performance impacts are workload-dependent, and, for the average computer user, should not be significant and will be mitigated over time.

    Intel is committed to the industry best practice of responsible disclosure of potential security issues, which is why Intel and other vendors had planned to disclose this issue next week when more software and firmware updates will be available. However, Intel is making this statement today because of the current inaccurate media reports.

    Check with your operating system vendor or system manufacturer and apply any available updates as soon as they are available. Following good security practices that protect against malware in general will also help protect against possible exploitation until updates can be applied.

    Intel believes its products are the most secure in the world and that, with the support of its partners, the current solutions to this issue provide the best possible security for its customers.

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    Parallel programming with Swift: Basics | real questions and Pass4sure dumps

    About a year ago my team started a new project. This time we wanted to use all our learning from prior projects. One of the decisions we’ve made was to make the entire model API asynchronous. This will allow us to change the entire implementation of the model, without affecting the rest of the app. If our app was able to handle asynchronous calls, it didn’t matter whether we were communicating with a backend, the cache or our database. It also enables us to work concurrently.

    At the same time, it had some implications. As developers, we had to understand topics like concurrency and parallelism. Otherwise,it would screw us royally. So let’s learn together how to program concurrently.

    Synchronous vs Asynchronous

    So what is really the difference between Synchronous and Asynchronous Processing? Imagine we have a list of items. When processing these items synchronously, we start with the first item and finish it before we begin the next. It behaves the same way as a FIFO Queue (First In, First Out).

    Translated into code it means: every statement of a method will be executed in order.

    So basically synchronous means to process 1 item completely at a time.

    In comparison, Asynchronous Processing handles multiple items at the same time. It would e.g. process item1, pause for item2 and then continue and finish with item1.

    An example in code would be a simple callback. We can see the code at the end being executed before the callback is processed.

    Concurrency vs Parallelism

    Often concurrency and parallelism are used interchangeably (even Wikipedia uses it wrong at some places…). This results in problems, which are easily avoidable if the differences are made clear. Let’s explain it with an example:

    Try to imagine, that we have a stack of boxes at position A and we want to transport them to position B. To do so, we can use workers. In a synchronous environment, we could only use 1 worker to do this. He would carry 1 box at a time, all the way from position A to position B.

    But let’s imagine we could use multiple workers at the same time. Each of them would take a box and carry it all the way. This would increase our productivity by quite a lot, wouldn’t it? Since we use multiple workers, it would increase by the same factor as the number of workers we have. As long as at least 2 workers carry boxes at the same time, they do it in parallel.

    Parallelism is about executing work at the same time.

    But what happens, if we have just 1 worker and might be able to use more than this? We should consider having multiple boxes in the processing state. This is what concurrency is about. It can be seen as dividing the distance from A to B in multiple steps. The worker could carry a box from A to the halfway point of the whole distance and then get back to A to grab the next box. Using multiple workers we could make them all carry the boxes a different distance. This way we process the boxes asynchronously. In case we have multiple workers, we process the boxes in parallel.

    So the difference between parallelism and concurrency is simple. Parallelism is about doing work at the same time. Concurrency is about the option to do work at the same time. It doesn’t have to be parallel, but it could be. Most of our computers and mobile devices can work in parallel (due to the number of cores) but every software you have definitely works concurrently.

    Mechanisms for Concurrency

    Every Operating System provides different tools to use concurrency. In iOS, we have default tools like processes and threads, but due to its history with Objective-C, there are also Dispatch Queues.


    Processes are the instances of your app. It contains everything needed to execute your app, this includes your stack, heap, and all other resources.

    Despite iOS being a multitasking OS, it does not support multiple processes for one app. Thus you only have one process. Looking at macOS it is a little bit different. You can use the Process class to spawn new child processes. These are independent of their parent process but contain all the information, the parent had at the time of the child process’s creation. In case you are working on macOS, here is the code to create and execute a process:


    A thread is some kind of lightweight process. Compared to processes, threads share their memory with their parent process. This can result in problems, such as having two threads changing a resource (e.g. a variable) at the same time. As a result we would be getting incoherent results, when reading it again. Threads are a limited resource on iOS (or any POSIX compliant system). It’s limited to 64 threads at the same time for one process. Which is a lot, but there are reasons to go above these. You can create and execute a thread this way:

    Dispatch Queues

    Since we only have one process and threads are limited to 64, there have to be other options to run code concurrent. Apple’s solution is dispatch queues. You can add tasks to a dispatch queue and expect it to be executed at some point. There are different types of dispatch queues. One is the SerialQueue. In this type everything will be processed in the same order as it was added to the queue. The other is the ConcurrentQueue. As the name suggests, tasks can be executed concurrently within this queue.

    This isn’t really concurrent yet, right? Especially when looking into SerialQueues, we didn’t win anything. And ConcurrentQueues don’t make anything easier. We do have threads, so what’s the point?

    Let’s consider what happens if we have multiple queues. We could just run a queue on a thread and then whenever we schedule a task, add this into one of the queues. Adding some brain power, we could even distribute the incoming tasks for priority and current workload, thus optimizing our system resources.

    Apple’s implementation of the above is called Grand Central Dispatch (or GCD for short). How is this handled in iOS?

    The great advantage of Dispatch Queues is, that it changes your mental model of concurrent programming. Instead of thinking in threads, you consider it as blocks of work pushed onto different queues, which is a lot easier.

    Operation Queues

    Cocoa’s high-level abstraction of GCD is Operation Queues. Instead of a block of discrete units of work you create operations. These will be pushed onto a queue and then executed at the correct order. There are different types of queues: the main queue, which executes on the main thread and the custom queues, which does not execute on the main thread.

    Creating an operation can also be done in multiple ways. Either you can create an Operation with a block, or subclass. In case you subclass, don’t forget to call finish, otherwise, the operation will never stop.

    A nice advantage about operations is that you can use dependencies. Having operation A depends on operation B results in B not being executed before A.

    Run Loops

    Run Loops are similar to Queues. The system runs through all the work in the queue and then starts over at the beginning. E.g. Screen redraw, is done by a Run Loop. One thing to note is, they aren’t really methods to create concurrency. Rather they are tied to a single thread. Still, they enable you to run code asynchronously, while alleviating you of the burden to consider concurrency. Not every thread has a Run Loop, instead, it will be created the first time it’s requested.

    While using Run Loops you need to consider that they have different modes. For example, when you scroll on your device, the Run Loop of the Main thread changes and delays all the incoming events. As soon as your device stops scrolling, the Run Loop will return to its default state and all the events will be processed. A Run Loop always needs an input source, otherwise, everything executed on it will immediately exit. So don’t forget about it.

    Lightweight Routines

    There is a new idea of having really lightweight threads. These are not yet implemented in Swift but there is a proposal at Swift Evolution (see Streams).

    Options to control Concurrency

    We looked into all the different elements provided by the Operating System, which can be used to create concurrent programs. But as mentioned above, it can create a lot of problems. The easiest problem to create and at the same time the hardest to identify is having multiple concurrent tasks accessing the same resource. If there is no mechanism to handle these accesses, it can result in one task writing one value. At the same time a second task would be writing a different value. When the first task reads the value again it would expect the value it has written itself, not the value of the other task. So the default way is to lock access to a resource and prevent other threads to access it as long as it is locked.

    Priority Inversion

    To understand the different locking mechanisms we also need to understand thread priorities. As you can guess, threads can be executed with higher and lower priorities, meaning everything on a higher priority will be executed earlier than lower priorities. When a lower priority thread is locking a resource a thread with higher priority wants to access, suddenly the thread with higher priority has to wait, thus (kind of) increasing the priority on the lower priority thread. This is called Priority Inversion and can result in the higher priority thread starving to death, as it never gets executed. So you definitely want to avoid it.

    Imagine having two high priority threads (1 & 2) and a low priority thread (3). If 3 blocks a resource 1 wants to access, 1 will have to wait. Since 2 has a higher priority, all its work will be done first. In cases, where this doesn’t end, thread 3 will not be executed and thus thread 1 will be blocked indefinitely.

    Priority Inheritance

    A solution to Priority Inversion is Priority Inheritance. In this case, thread 1 would surrender it’s priority to thread 3, as long as it is blocked. So thread 3 and 2 have a high priority and get both executed (depending on the OS). As soon as 3 unlocks the resource, the high priority is back to thread 1 and it will continue with its original work.


    Atomic contains the same idea as a transaction in a database context. You want to write a value all at once behaving as one operation. Apps compiled for 32 bit, can have quite the odd behavior, when using int64_t and not having it atomic. Why? Let’s look into detail what happens:

    int64_t x = 0 Thread1:x = 0xFFFF Thread2:x = 0xEEDD

    Having a non-atomic operation can result in the first thread starting to write into x. But since we are working on a 32bit Operating System, we have to separate the value we write into x into two batches of 0xFF.

    When Thread2 decides to write into x at the same time, it can happen to schedule the operations in the following order:

    Thread1: part1Thread2: part1Thread2: part2Thread1: part2

    In the end we would get:

    x == 0xEEFF

    which is neither 0xFFFF nor 0xEEDD.

    Using atomic we create a single transaction which would result in the following behavior:

    Thread1: part1Thread1: part2Thread2: part1Thread2: part2

    As a result, x contains the value Thread2 set. Swift itself does not have atomic implemented. On Swift evolution is a proposal to add it, but at the moment, you’ll have to implement it yourself.


    Locks are a simple way to prevent multiple threads to access a resource. A thread first checks, whether it can enter the protected part or not. If it can enter, it will lock the protected part and proceed. As soon as it exits, it will unlock. If on entering the thread encounters a locked part, it will wait. This is normally done by sleeping and regularly waking up, to check whether it is still locked or not.

    In iOS, this can be done with NSLock. But be aware, when unlocking, it has to be the same thread, as the one that locked.

    There are also other types of locks, such as recursive locks. With these, a thread can lock a resource multiple times and has to release it as often as it locked. During this whole time, other threads are excluded.

    Another type is the read-write lock. This is useful for large-scale apps when a lot of threads read from a resource and only write sometimes. As long as no thread is writing to the resource all threads can access it. As soon as a thread wants to write to it, it will lock the resource for all threads. They can’t read until the lock is released.

    On the process level, there is also a distributed lock. The difference is, in case the process is blocked, it just reports it to the process and the process can decide how to handle this situation.


    A lock consists of multiple operations which send threads asleep, till it’s the threads turn again. This results in context changes for the CPU (pushing registers etc. to store the threads state). These changes need a lot of computation time. If you have really small operations you want to protect, you can use spinlocks. The basic idea is to make the waiting thread poll the lock, as long as it is waiting. This requires more resources, than a sleeping thread. At the same time, it circumvents the context changes and is thus faster on small operations.

    This sounds nice in theory, but iOS is as always different. iOS has a concept called Quality of Service (QoS). With QoS, it can happen that low priority threads will not be executed at all. Having a spinlock set on such a thread and a higher thread trying to access it, will result in the higher thread starving the lower thread, thus not unlocking the required resource and blocking itself. As a result, spinlocks are illegal on iOS.


    A mutex is like a lock. The difference is, it can be across processes and not only across threads. Sadly you will have to implement your own Mutex since Swift doesn’t have one. This can be done using C’s pthread_mutex.


    A semaphore is a data structure to support mutual exclusivity in thread synchronization. It consists of a counter, a FIFO queue and the methods wait() and signal().

    Every time a thread wants to enter a protected part, it will call wait() on the semaphore. The semaphore will decrease it’s counter and as long as it is not 0, will allow the thread to continue. Otherwise, it will store the thread in its queue. Whenever a thread exits a protected part, it will call signal() to inform the semaphore. The semaphore will first check, whether there is a thread waiting in its queue. If this is the case, it will wake the thread, so it can continue. If not, it will increase its counter again.

    In iOS, we can use DispatchSemaphores to achieve this behavior. It’s preferred to use these over the default Semaphores, as they only go down to kernel level in case it really needs to. Otherwise, it behaves a lot faster.

    One might consider a binary semaphore (a semaphore with counter value 1) to be the same as a mutex, but while a mutex is about locking mechanism, a semaphore is a signaling mechanism. This doesn’t really help, so where is the difference?

    A locking mechanism is about protecting and managing access to a resource. So it prevents multiple threads to access one resource at the same time. A signaling system is more like calling “Hey I’m done! Carry on!”. For example, if you are listening to music on your mobile phone and a call comes in, the shared resource (headphones) will be acquired by the phone. When it is done, it will inform your mp3 player via a signal to continue. This is the situation to consider a semaphore over a mutex.

    So where is the catch? Imagine you have a low priority thread (1) which is within the protected area, and you have a high priority thread (2) which just called wait() on the semaphore. 2 is sleeping and waiting for the semaphore to wake it up. Now we have a thread (3) which has a higher priority than 1. This thread in combination with QoS prevents 1 to signal the semaphore and thus starves both other threads. So the semaphores within iOS do not have Priority Inheritance.


    In Objective-C, there is also the option to use @synchronized. This is an easy way to create a mutex. Since Swift doesn’t have it, we have to look a little bit deeper. You’ll find out, @synchronized just calls objc_sync_enter.

    Since I’ve seen this question multiple times on the internet let’s answer it too. As far as I know, this is not a private method, so using it won’t exclude you from the AppStore.

    Concurrency Queues Dispatching

    Since there is no mutex in Swift and synchronized has also been removed, it became the golden Standard for Swift developers to use DispatchQueues. When using it synchronously, you have the same behavior as a mutex, as all the actions are queued on the same queue. This prevents it from being executed simultaneously.

    The disadvantage is it’s time consumption as it has to allocate and change contexts a lot. This is irrelevant if your app doesn’t need any high computational power, but in case you experience any frame drops, you might want to consider a different solution (e.g. Mutex).

    Dispatch Barriers

    If you are using GCD, there are more options to synchronize your code. One of these are Dispatch Barriers. With these, we can create blocks of protected parts, which need to be executed together. We can also control in which order asynchronous code executes. It sounds odd to do this, but imagine you have a long running task to do, which can be split into parts. These parts need to be run in order but can again be split into smaller chunks. These smaller chunks of a part can be run asynchronously. Dispatch Barriers can now be used to synchronize the larger parts, while the chunks can run wild.


    A trampoline is not really a mechanism provided by the OS. Instead, it is a pattern you can use to ensure a method is called on the correct thread. The idea is simple, the method checks at the beginning, whether it is on the correct thread, otherwise, it calls itself on the correct thread and returns. Sometimes you need to use the above locking mechanisms, to implement a waiting procedure. This is only the case, whenever the method called returns a value. Otherwise, you can simply return.

    Don’t use this pattern too often. It’s tempting to do so and ensure your thread, but at the same time, it confuses your coworkers. They might not understand why you are changing threads everywhere. At some point, it becomes clutter and takes away the time to reason about your code.


    Wow, this was quite a heavy post. There are so many options to do concurrent programming and this posts just scratches the surface. At the same time, there are so many mechanisms to do so and a lot of cases to consider. I’m probably annoying everyone at work, whenever I talk about threads, but they are important and slowly my coworkers start to agree. Just today I had to fix a bug where operations accessed an array asynchronous and as we’ve learned Swift doesn’t support atomic actions. Guess what? It ended up in a crash. This might not have happened if all of us would know more about concurrency, but truth be told, I didn’t see it at first either.

    Knowing your tools is the best advice I can give you. With the above post, I hope you found a starting point for concurrency and also a way to control the chaos which will manifest as soon as you dive deeper. Good Luck!

    P.S.: There is more to come: An in-depth look into Operations and other higher level tools to battle concurrency!

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