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700-038 Advanced Collaboration Architecture(R) field Engineer

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700-038 exam Dumps Source : Advanced Collaboration Architecture(R) field Engineer

Test Code : 700-038
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Cisco Cisco Advanced Collaboration Architecture(R)

custom computing device specialists Renews Cisco superior Collaboration… | killexams.com true Questions and Pass4sure dumps

customized laptop specialists Renews Cisco superior Collaboration architecture Specialization

HAUPPAUGE, N.Y. (PRWEB) July 18, 2018

customized laptop experts (“custom”), a leading expertise options company, announced nowadays it has renewed its Cisco superior Collaboration architecture Specialization. This specialization acknowledges customized as having again fulfilled the practicing requirements and application necessities to promote, set up and assist extremely subtle applications-primarily based Cisco Collaboration solutions.

"it's an reverence to bag hold of this mountainous difference," observed Kyriakos Kaimis, vice chairman of expertise at custom. "customized is steadfastly invested in the americans, techniques, and expertise that attend clients power enterprise productiveness. This specialization permits custom to deliver robust, collaboration options to their customers.”

As a Cisco advanced Collaboration Specialization companion, customized has established its skill to provide sophisticated, cost-brought Cisco solutions via in-depth revenue capabilities, know-how talents and repair offerings. Cisco superior Specialization companions work with modern and present technologies to align add-ons of those architectures with their customers’ strategic dreams, helping transform company strategies, enhance organizational efficiency and precipitate up the time to market.

The Cisco Channel companion program gives companions with the working towards required to construct income, technical and Cisco Lifecycle functions talents, after which validates their talents through a 3rd-birthday celebration audit. Cisco Channel accomplice certifications—choose, Premier, and Gold—symbolize an increasing breadth of abilities throughout key technologies and a partner’s capacity to bring built-in networking solutions. Cisco Channel associate specializations—SMB, express, advanced and master—reflect an expanding depth of income, technical and service abilities in selected applied sciences. Cisco advanced Specializations provide custom entry to complete sales, technical, and lifecycle features practising and pilot purchasable from Cisco.

About custom desktop SpecialistsFounded in 1979, customized desktop consultants helps Northeast public and private sector valued clientele bag maximum expense from their IT investments. custom’s pleasing aggregate of privately owned flexibility and wide IT potential empowers it to architect customer-centric solutions that bring effects. http://www.customtech.com

Cisco, the Cisco brand and Cisco methods are registered trademarks of Cisco systems Inc. in the united states and inevitable other international locations.

###

Contact author

MaryAnn Benzola custom laptop experts, INC.+1 (631) 761-1465Email > visit site


LaSalle options once again Achieves advanced Collaboration structure Specialization From Cisco in the united states | killexams.com true Questions and Pass4sure dumps

ROSEMONT, IL--(Marketwired - March 03, 2015) - To aid the increasing duty of collaboration options that leverage the intelligence of the network, LaSalle options announced nowadays that it has executed the superior Collaboration architecture Specialization from Cisco. This specialization recognizes LaSalle options as having fulfilled the practicing requirements to promote, design and installation comprehensive Cisco® Collaboration architecture solutions.

As a Cisco superior Collaboration architecture really superb partner, LaSalle options has invested in the practising required to bring differentiated enterprise expense throughout the integrated, open groundwork of the collaboration structure. Cisco advanced Collaboration structure specialized companions work with modern and current applied sciences to align add-ons of this structure with their valued clientele' strategic dreams, assisting seriously change enterprise procedures, increase organizational effectivity and accelerate the time to market.

"we're proud to once again achieve the Cisco superior Collaboration architecture Specialization," says Steven Robb, President of the solutions group at LaSalle solutions. "This carrying on with training and partnership is a mutual ongoing dedication, as Cisco requires annual renewal for this and many other specializations. we're proud to proceed their dedication, and suppose this recognition reflects their dedication to featuring the team, strategies and tools to convey the sophisticated options their purchasers possess Come to matter on, and permit us to exceed expectations to fulfill brand modern enterprise challenges and construct their aggressive edge."

The Cisco Resale Channel software provides partners with the practicing required to construct sales, design and technical skill after which validates their skills via a 3rd-celebration audit.

This recertification builds on a few Cisco-related milestones LaSalle options has in the past accomplished, together with:

  • Cisco US features confederate of the 12 months: present
  • client satisfaction Excellence Gold renowned person: current, forty Consecutive Quarters. 
  • Cisco® Gold certified associate
  • Cisco master Unified Communications Specialization
  • Cisco grasp safety Specialization
  • international companion network accomplice
  • superior statistics middle architecture Specialization
  • superior borderless network structure Specialization 
  • ATP - Cisco TelePresence Video superior
  • ATP - statistics Virtualization Reseller
  • ATP - power management Suite Integrator
  • ATP - identification functions Engine
  • Cisco functions confederate of the year, faultfinding place: 2010 - 2013
  • About LaSalle options

    situated in 1980, LaSalle solutions is a number one provider of lifestyles-cycle administration features for technology and capital property. These services include acquisition and financing, IT asset management, protection shrink administration, remarketing and disposition. LaSalle options' processes, fabulous client service and strong, market-main cloud-primarily based toolset, LAMP, enable consumers to greater economically and comfortably exploit and arrangement to satisfy their desires.

    LaSalle solutions is an independently operated enterprise and a subsidiary of MB economic financial institution, a publicly traded Chicago-based mostly bank maintaining business. MB fiscal is traded on the NASDAQ as "MBFI".

    For extra tips on LaSalle solutions, tickle consult with www.elasalle.com and www.YouTube.com/LaSalleSolutions.

    LaSalle solutions and LAMP are registered emblems of LaSalle options in the u.s.. Cisco and the Cisco brand are trademarks or registered emblems of Cisco and/or its affiliates within the U.S. and other nations.


    LaSalle solutions Renews Cisco advanced Collaboration architecture Specialization | killexams.com true Questions and Pass4sure dumps

    March 06, 2018 15:00 ET | supply: LaSalle solutions

    ROSEMONT, unwell., March 06, 2018 (GLOBE NEWSWIRE) -- LaSalle solutions, a number one issuer of expertise lifecycle administration services, announced nowadays that it has renewed its Cisco superior Collaboration architecture Specialization. The specialization acknowledges that LaSalle has again fulfilled the practising necessities and application must haves to sell, design and set up complete Cisco Collaboration options.

    As a Cisco advanced Collaboration Specialization associate, LaSalle solutions has demonstrated its capability to supply sophisticated, value-added Cisco solutions via in-depth earnings capabilities, expertise advantage and service offerings. Cisco advanced Specialization companions work with modern and existing applied sciences to align accessories of these architectures with their valued clientele’ strategic dreams, helping seriously change enterprise procedures, boost organizational efficiency and precipitate up the time to market.

    “we are proud to once again obtain superior Collaboration structure Specialization from Cisco,” referred to Steven Robb, president of the solutions community at LaSalle solutions. “Our valued clientele appear to us for assist improving collaboration across their businesses. This specialization is because of the the difficult work LaSalle solutions places in every yr to breathe positive that they now possess the premier technologies and potential to increase customer collaboration options to extra sustainable, unified solutions.”

    About LaSalle solutions

    centered in 1980, LaSalle solutions is a leading provider of expertise lifecycle asset management functions. LaSalle allows its shoppers to improve their expertise operations via better approaches, administration and reporting for improved planning and recrudesce on investment. LaSalle options’ tactics, outstanding client service and robust, market-leading cloud-based toolset, LAMP, allow valued clientele to attain more desirable enterprise outcomes via transparency and respectable results at their fingertips.

    LaSalle options is a division of MB gadget Finance LLC, a subsidiary of MB economic financial institution, N.A., a commerce bank headquartered in Chicago. MB fiscal Inc. is the publicly traded keeping commerce for MB fiscal bank, N.A. and is traded on the NASDAQ as “MBFI.”

    For extra suggestions on LaSalle options, tickle seek advice from www.elasalle.com and www.YouTube.com/LaSalleSolutions.

    LaSalle options and LAMP are registered emblems of LaSalle options within the united states.

    Press Contact Beth Kirshenberg LaSalle options 847.823.9600

    Rosemont, Illinois, u.s.

    Press Contact Beth Kirshenberg LaSalle options 847.823.9600 LaSalle Solutions Logojpg_1200pxw.jpg

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    700-038 Advanced Collaboration Architecture(R) field Engineer

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    Killexams.com 700-038 Dumps and true Questions

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    Test Code : 700-038
    Test name : Advanced Collaboration Architecture(R) field Engineer
    Vendor name : Cisco
    exam questions : 50 true Questions

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    ZF is using the Xilinx® Zynq® UltraScale+™ MPSoC platform to handle real-time data aggregation, pre-processing, and distribution, as well as to provide compute acceleration for the AI processing in ZF's modern AI-based electronic control unit. ZF selected this adaptable, intellectual platform because it provides the processing power scalability and flexibility essential for the ZF ProAI platform to breathe customized for each of its customer's unique requirements. 

    "The unique selling proposition of the ZF ProAI is its modular hardware concept and open software architecture. Their aim is to provide the widest viable ambit of functions in the field of autonomous driving," explained Torsten Gollewski, head of ZF Advanced Engineering and universal manager of Zukunft Ventures GmbH. This approach is unique compared to other systems on the market, which exhaust a fixed combination of hardware and software architecture – a solution that can potentially confine functionality and add more cost.

    "We are proud to confederate with ZF on its ProAI platform and attend solve the challenges associated with autonomous vehicle development," said Yousef Khalilollahi, vice president, core plumb markets, Xilinx. "By providing an adaptable hardware platform, ZF can design flexible and scalable systems that seamlessly incorporate AI compute acceleration and functional safety (FuSa) through diversity in processing engines. They observe forward to expanding their collaboration with ZF to capture autonomous and AI innovation to the next level."

    Xilinx has been selling chips to automakers and Tier 1 automotive suppliers for over 12 years. More than 160 million Xilinx devices are in automotive systems today, and approximately 55 million of these are used for ADAS alone.

    About XilinxXilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies – from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP, designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intellectual and connected world of the future. For more information, visit www.xilinx.com.

    About ZF Friedrichshafen AG ZF is a global leader in driveline and chassis technology as well as vigorous and passive safety technology. The company has a global workforce of 146,000 with approximately 230 locations in some 40 countries. In 2017, ZF achieved sales of €36.4 billion and as such, is one of the largest automotive suppliers worldwide.

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    © Copyright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, Zynq and other designated brands included herein are trademarks of Xilinx in the United States and other countries. totality other trademarks are the property of their respective owners.

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    Automation programming advances enhance communication, programming capabilities | killexams.com true questions and Pass4sure dumps

    Automation software and hardware advances reduce programming tasks and provide more built-in configurability, scalability, background communication among software components, simulation/digital twin capability, and usability.

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    HMI animations

    Dynamic HMI content makes it easier to visualize intricate manufacturing processes. One approach uses a widget to allow users to animate XML-based scalable vector graphics (SVG) images they already possess or to transfigure them from 2-D CAD with runtime data.

    The user drags and drops a widget onto the desired page in the HMI application and configures it there. At runtime, the image’s animation can breathe controlled from the application program. Rotations, transitions, and movements can breathe animated from one SVG image, which saves the time and cost needed to create sequences of multiple images. Also, since SVG images are based on vector graphics, they retain their tall resolution without loss of character even when zoomed in.

    Figure 1: Dynamic human-machine interface (HMI) content such as scalable vector graphics (SVG) makes it easier to visualize intricate manufacturing processes. Courtesy: B&R Automation

    Figure 1: Dynamic human-machine interface (HMI) content such as scalable vector graphics (SVG) makes it easier to visualize intricate manufacturing processes. Courtesy: B&R Automation

    Managing machine variants

    Modular applications can breathe implemented to add I/O modules to existing programs at any time without touching the machine code. This can chance before a machine is delivered or even at runtime, which simplifies managing machinery and paraphernalia variants. I/O variant configurations can breathe generated from enterprise resource planning (ERP) or an order management system. No engineering tools are required even if third-party drives or modules are added.

    Additional variants and options may breathe configured directly on the machine using the confiscate configuration tools. Some evolution environments include a utensil that allows the programming of options in ladder logic without affecting the machine’s primary application. The machine can breathe commissioned without having to modify the original machine software, giving the End user needed flexibility while preserving the integrity of the original paraphernalia manufacturer (OEM) solution.

    Figure 2: Input/output (I/O) machine variant configurations can breathe generated directly from an enterprise resource planning (ERP) or order management system and no engineering tools are required. Courtesy: B&R Automation

    Figure 2: Input/output (I/O) machine variant configurations can breathe generated directly from an enterprise resource planning (ERP) or order management system and no engineering tools are required. Courtesy: B&R Automation

    Integrated vision

    Another trend is integrating vision cameras into the machine control program, including intellectual cameras, lighting, and advanced image processing algorithms. This allows microsecond synchronization between the machine vision and other automation components with one engineering utensil and one application to manage.

    PDF reports

    Communication platforms can breathe built into the control system, and they automatically can generate PDF reports. Reporting functionalities collect statistical machine data and information from any software components provided by the control platform. The data, layout, and design of the reports can breathe customized and the user can define the language and units used.

    Report design options invent it viable to customize reports to the users’ needs. Graphical elements such as images and tables can breathe included in the reports. To protect against unauthorized access, it is viable to encrypt the files. The reports can breathe sent automatically via e-mail at a defined time or triggered by a specific event. In addition, reports can breathe saved to external storage media such as a USB flash drive or sent directly from the machine to network printers.

    Figure 3: Communication platforms can breathe built into the control system, and they can automatically generate PDF reports. There are options available to customize reports to the specific needs of different users. Courtesy: B&R Automation

    Figure 3: Communication platforms can breathe built into the control system, and they can automatically generate PDF reports. There are options available to customize reports to the specific needs of different users. Courtesy: B&R Automation

    Data management

    Implementing databases in applications is easier with a database integration toolbox. Data may breathe archived from the field level to a database, regardless of whether that database is located on-site or in the cloud. This simplifies managing great volumes of data, which is key to Industrial Internet of Things (IIoT) data acquisition and analytics requirements.

    Manufacturing machinery can generate huge volumes of data, which must breathe visualized, archived, or passed on to higher-level systems for processing to breathe useful. Giving the control system a database interface makes it viable to forward data directly from the controller to the database. Common database functions such as stored procedures allow key performance indicators (KPIs) to breathe generated as needed, resulting in more optimized manufacturing processes.

    Figure 4: With a database integration toolbox, it is viable
 to archive data directly from the field level to a database, which helps simplify managing great
 volumes of data. Courtesy: B&R Automation

    Figure 4: With a database integration toolbox, it is viable to archive data directly from the field level to a database, which helps simplify managing great volumes of data. Courtesy: B&R Automation

    Machine simulation and digital twins

    Automation programming is no longer limited to isolated machine programs. It now includes integrated production systems such as the next generation of intellectual track technologies that define the adaptive machine.

    Consider the automation software challenge of independently controlling individual products traveling on shuttles in coordination with dozens or even hundreds of other shuttles on a track system. Each workstation represents a machine module, and totality the machine control and ancillary functions apply for each product, production module, and the overall system.

    Built-in simulation software is a valuable utensil to visualize and optimize intellectual track system requirements. It facilitates engineering and reduces time to market for modern track systems and for running modern products on existing systems. Integrated simulation software is based on process-oriented programming.

    These simulation tools attend ensure shuttles achieve not collide, cross virtual barriers, or violate configurable precipitate limits. FDA-compliant tracking likewise can breathe implemented. The software can link the product data with the respective shuttles and invent the manufacturing process traceable.

    When track system applications are created using process-oriented programming, a software engineer simply defines rules for how the shuttles should behave on the track. The rules become vigorous when shuttles pass virtual trigger points. This makes motion sequence implementation more efficient and reduces the amount of programming required for the individual shuttles.

    With integrated simulation options, a track system developer can race tests to identify the optimum number and precipitate to maximize shuttle productivity. The selfsame system software is used in the simulation and the true plant, which makes it viable to switch between simulation and true operation at any time. How the shuttles interact with mechanical elements, such as robots, likewise can breathe visualized.

    Figure 5: Automation programming now includes integrated production systems such as the next generation of intellectual
 track technologies that define the adaptive machine. Courtesy: B&R Automation

    Figure 5: Automation programming now includes integrated production systems such as the next generation of intellectual track technologies that define the adaptive machine. Courtesy: B&R Automation

    Selecting the privilege integrated automation platform

    These examples available to the machine automation programmer demonstrate how far beyond stand-alone machine operation today’s software considerations—and tools—extend. It’s no longer a question of choosing ladder logic versus C programming. It’s about selecting an integrated automation platform that delivers a configurable software suite to manage—not just control—machines.

    For an architect to develop these functions on a one-off machine project basis would breathe daunting at best, and impractical in reality. At the selfsame time, these kinds of modern software functions are essential to realize the connected machine, let lonesome manufacturing IIoT, and are designed to deliver machinery to back the modern digital commerce models.

    John Kowal is director, commerce development, B&R Industrial Automation Corp. Edited by Chris Vavra, production editor, Control Engineering, CFE Media, cvavra@cfemedia.com.

    MORE ANSWERS

    Keywords: Automation software, human-machine interface, automation programming

    Automation hardware and software today are no longer stand-alone functions; they encompass almost every aspect of the manufacturing floor.

    Advances include integrated vision, automated data reports, managing machine variants, and improved simulation.

    Automation software advances are essential to delivering the modern digital commerce models for today’s interconnected manufacturing environment.

    Consider this

    What other advances in automation programming could provide major benefits to manufacturers?


    What’s the privilege Path For Scaling? | killexams.com true questions and Pass4sure dumps

    The growing challenges of traditional chip scaling at advanced nodes are prompting the industry to capture a harder observe at different options for future devices.

    Scaling is noiseless on the list, with the industry laying plans for 5nm and beyond. But less conventional approaches are becoming more viable and gaining traction, as well, including advanced packaging and in-memory computing. Some options are already here, while others are noiseless in R&D and require more funding to bag off the ground. Some may never work.

    Nevertheless, the industry is looking for solutions, whether that involves IC scaling or novel approaches.

    Chip scaling is being pursued by several chipmakers and foundry customers. For this, chipmakers are ramping up 10nm/7nm, with 5nm and 3nm in R&D. But at each node, the costs are escalating, signification that only a select few with abysmal pockets can afford to migrate to the next step. Plus, the benefits of scaling are shrinking at each node, and the traditional approach is no longer suitable for totality devices.

    Even Intel, which created Moore’s Law, is coming to grips with the issues and is re-thinking the artery chips are developed amid the shift towards 5G, artificial intelligence and machine learning.

    “In the previous generations, the retort has been that transistor density and Moore’s Law will play the lead role to solve computing problems,” said Raja Koduri, senior vice president of Core and Visual Computing at Intel. “But as the process node transitions possess slowed from the pace of the previous decades, it is the essence of Moore’s Law that continues to provide modern technologies and capabilities to meet the demands of modern computing. The message of Moore’s Law is about more than transistors alone, with the combination of transistors, architectural research, connectivity advancements, faster reminiscence systems, and software working together to drive it forward.”

    This is not to voice Intel or others possess stopped scaling. But in addition to monolithic device scaling, the industry is looking at modern ways to walk the ball forward. For example, a growing list of entities are throwing their weight behind the chiplets model. Intel and TSMC are the latest backers of chiplets.

    “What we’ve done over the ultimate 15 to 20 years is to let the leading edge—the fast-path computing Part of whatever product you’re designing—push the technology, and everything else they want to integrate on that chip comes along with it,” said David Fried, CTO at Coventor, a Lam Research Company. “You can achieve you I/O circuits, your low-speed data path, memory, power conservation. Okay, it’s going to breathe in the advanced technology, but that’s not really why they did the advanced technology in the first place. We’re noiseless doing something similar. A lot of these high-end applications are noiseless driving the front-end of technology, but instead of just dragging along reminiscence we’re going to heterogeneous integration. Instead of just dragging along the I/O or the analog part, we’re going to some 3D stacking to attach those together. So everything is customized, but only because we’ve kindhearted of stopped just dragging them along into the most advanced technology.”

    In this changed environment, chipmakers and foundry customers must retain a proximate eye on the various manufacturing and related options to enable future devices. Some may exhaust more than one option as there is no one technology that fits totality applications. And, of course, not totality will migrate to advanced nodes.

    Among the leading options:

  • Gate-all-around. A modern transistor character targeted for 3nm in 2020.
  • Monolithic 3D. A fashion of stacking transistors on each other.
  • Near- and in-memory computing. Near-memory incorporates reminiscence in a package. In-memory has various meanings, but in some circles, the thought is to perform the computational tasks within a memory.
  • Advanced packaging. The thought is to integrate dies in a package. Chiplets tumble into this category. With chiplets, you possess a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme.
  • Going to gate-all-aroundFor more than half a century, the growth engine has revolved around Moore’s Law, the axiom that states transistor density would double every 18 to 24 months. Adhering to Moore’s Law, chipmakers introduced a modern process in that time interval to lower the cost per transistor.

    At each node, chipmakers scaled the transistor specs by 0.7X, enabling the industry to deliver a 40% performance boost for the selfsame amount of power and a 50% reduction in area. That formula worked until 20nm, when traditional planar transistors ran out of steam due to technical issues. In response, Intel moved to finFETs at 22nm, followed by the foundries at 16nm/14nm. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

    Before 14nm, there was a 30% improvement in price/performance at each node, according to analysts. From 14nm to 10nm, there is more than 20% improvement, and at less than 10nm there is more than 20%. At 3nm, there is about 20% improvement, analysts said.

    However, the industry was forced to walk from planar to finFETs at 20nm. The industry faced short channel effects and other issues at 20nm. In other words, finFETs solved those problems, but it’s debatable if you bag the traditional scaling improvements at each node.

    FinFETs achieve provide more performance with lower power, but it becomes more difficult to scale them at each node. As a result, the cadence for a fully scaled node has extended from 18 months to 2.5 years or longer. In addition, fewer foundry customers can afford to walk to advanced nodes. IC design costs possess jumped from $51.3 million for a 28nm planar device to $297.8 million for a 7nm chip and $542.2 million for 5nm, according to IBS.

    “PPAC (power, performance, area, cost) scaling at the leading edge is getting more intricate and costly,” said Yang Pan, corporate vice president of advanced technology evolution at Lam Research. “As process complexity increases, managing process-to-process interaction through advanced process control is a must to reduce variation.”

    Over time, the market split into two camps. One involves IC suppliers that don’t require finFETs or can’t afford them. This includes analog, mixed-signal and RF, which exhaust ripen processes. That market is thriving.

    For example, several foundries proffer finFET processes. Yet, demand is robust for ripen processes at 40nm and above. “UMC is experiencing tall demand from ripen 12-inch processes,” said Jason Wang, co-president of UMC. “With modern applications in 5G, IoT, automotive and AI requiring these technologies, they anticipate the market conditions driving this demand to remain stalwart for the foreseeable future.”

    Even 200mm fab capacity and chips are noiseless in tall demand. “For the 8-inch, they possess to remain optimistic and cautious about the 8-inch outlook. They possess pretty superb assurance that they will remain fully loaded in Q4 2018,” Wang said in a recent conference call.

    The second camp involves companies that continue to scale and require high-performance chips. “Moore’s Law is definitely slowing down, but I’m confident there will breathe continued innovation everywhere to retain it going for a while,” said Aki Fujimura, chief executive of D2S. “Regardless, there’s no question there is a need for more compute power. There was some talk of how they can no longer exhaust more compute power perhaps 10 years ago. There’s no more talk about that now.”

    For years, IC scaling has been the main artery to boost transistor density and enable high-performance chips. Today, 7nm is the most advanced process. By most accounts, 7nm is expected to breathe a long-running node, as it provides enough PPAC for most apps.

    Still, TSMC plans to extend the finFET to 5nm, which is slated for 2020. But finFETs will likely race out of steam at 5nm, signification the industry will require a modern transistor character at or around 3nm.

    Moving to a modern transistor character isn’t simple. It requires modern tools, materials and integration schemes. Plus, the IC design costs will breathe astronomical at 3nm, so the mountainous question is whether anybody will migrate to this node.

    “Initially, there will breathe the accustomed suspects working with 3nm, such as Nvidia, Xilinx, Apple and Samsung,” said Joanne Itow, an analyst with Semico Research. “Once they bag totality the kinks worked out, you’ll see Qualcomm, MediaTek, AMD, Intel (Altera) and others jumping on board.”

    The industry has been working on next-generation transistors in R&D, and for 3nm it has narrowed the field to two technologies, nanosheet and nanowire FETs. Both are classified as gate-all-around technologies. They implement a gate on four sides of the structure, enabling more control of the current.

    The nanosheet FET is the current favorite. It has a wider channel than the nanowire, enabling more drive current. Plus, the nanosheet is an evolutionary step from a finFET, signification it uses many of the selfsame process steps. In a nanosheet, a finFET is placed on its side and is then divided into divorce horizontal pieces, which invent up the channels. A gate wraps around each channel.

    Fig. 1: Cross-section simulation of (a) finFET, (b) nanowire, and (c) nanosheet. Source: IBM

    In 2017, Samsung introduced what it calls a Multi Bridge Channel FET (MBCFET), which is a nanosheet FET. Targeted for 3nm, Samsung’s MBCFET is slated for production in 2020. Intel and TSMC haven’t announced their plans beyond finFETs.

    At the recent IEDM conference, Samsung presented its first results with MBCFET, aphorism it has developed a functional SRAM device. “Three representative superior characteristics of MBCFET compared to finFET possess been demonstrated — better gate control with a 65mV/decade sub-threshold swing at a short gate length; higher DC performance with a larger efficient channel width at a reference footprint; and design flexibility with variable nanosheet widths,” said Geumjong Bae, a researcher at Samsung.

    A nanosheet FET enables the industry to vary the width of the channels or sheets in devices. For example, a nanosheet FET with a wider sheet provides more drive current and performance. A narrow nanosheet has less drive current, but it takes up less area.

    All told, nanosheet FETs enable the industry to scale a device when finFETs hit the wall. But nanosheets provide only marginal gate-pitch scaling benefits. Design costs are the other mountainous issue.

    What is monolithic 3D?The industry has been working on alternatives, as well, including monolithic 3D—sometimes called 3D sequential integration.

    In simple terms, you develop a layer of transistors on one substrate. The transistor character depends on the application, but you could exhaust analog, logic or memory. Then, you develop another layer of transistors on another substrate. The two layers are bonded and connected using tiny interconnects, and the End result is a 3D monolithic device. The technology has demonstrated up to a 50% district reduction in devices, according to Imec.

    DARPA, Imec, Leti and others are pursuing the technology in R&D, although it’s unclear when it will appear in the market because there are several challenges to solve. For instance, the top layer requires various process steps with temperatures around 500°C. Otherwise, the top layer can demean the bottom tier. So the industry requires tools that work at lower temperatures, which has been the primary roadblock.

    There are reports of progress. For example, using a 3D sequential process with temperatures at 520°C, Imec stacked two layers of finFETs on top of each other. The finFETs possess a 45nm pitch and 110nm gate pitch.

    Fig. 2: Stacking finFETs on finFETs Source: Imec

    In sequential processing, you possess a substrate, based on either bulk CMOS or silicon-on-insulator (SOI) technology. Then, you build two tiers (bottom and top) on the substrate. In the flow, you first build the bottom tier with a layer of transistors.

    “You build your first layer of the device. They did it with bulk finFET, but it could breathe any technology,” said Anne Vandooren, principal member of the technical staff at Imec.

    Then, a level of interconnects are processed on that layer. The next step is to fabricate the top with a layer of transistors. The bottom and top layers are bonded.

    This isn’t limited to finFETs. “It really depends on the application. It can breathe a CMOS logic cell on a CMOS logic cell. Or it could breathe another application enjoy RF on logic, sensor on logic, reminiscence on logic, or logic on memory,” Vandooren said.

    Leti, meanwhile, has been working on a similar technology, and has recently developed some modern capabilities. First, Leti has demonstrated a low-resistance polysilicon gate for the top transistors. The layer was processed using a nanosecond laser anneal tool, which works at higher temperatures without impacting the bottom level. The R&D organization likewise has developed an epi process at 500°C. It has developed other processes, as well.

    “This integration scheme offers a wide spectrum of applications, including for example: 1) increasing integration density beyond device scaling; 2) enabling neuromorphic integration where RRAM is placed between top and bottom tiers; and 3) enabling low-cost heterogeneous integration for smart sensing arrays,” said Maud Vinet, advanced CMOS laboratory manager at Leti.

    Processing in memoryThere are other approaches, as well, namely using a memory-centric technology. Today’s reminiscence hierarchy is straightforward. SRAM is integrated into the processor for cache. DRAM is used for main memory. And disk drives and NAND-based solid-state storage drives (SSDs) are used for storage.

    In systems, data moves between the reminiscence and a processor. But at times this exchange causes latency and power consumption, which is sometimes referred to as the reminiscence wall.

    DRAM is one of the culprits. The data rates for DRAM possess fallen behind in terms of bandwidth.

    The industry has been working to resolve this problem for years. The latest solutions involve two technologies—near-memory computing and in-memory computing. “The growing trend of near-memory computing and in-memory computing will drive modern architectures that are integrating logic (digital and analog) and modern memories,” Lam’s Pan said.

    Near-memory computing isn’t new. It involves integrating high-bandwidth reminiscence (HBM) in a package, enabling faster data access and lower power consumption. For example, in a 2.5D package, a vendor could incorporate a graphics processor and HBM, which stacks DRAM dies on top of each other to enable more I/Os.

    In-memory computing, sometimes called processing in-memory, likewise is emerging. This concept means different things to different people. In some circles, in-memory computing involves a process in which the computations are performed within the reminiscence and/or at the location of the data storage.

    The thought has been around for years, but the early efforts fell short. Today, chipmakers, startups, R&D organizations and universities are working on the technology and making progress.

    “There are products coming out in that direction. In-memory computing is happening now using existing reminiscence technology. The products are being built specifically for those applications. That will drive more segmentation in reminiscence applications,” said Gill Lee, managing director of reminiscence technology at Applied Materials.

    For example, startup Mythic recently introduced a matrix multiply reminiscence architecture. It performs the computations inside the reminiscence cells using analog currents and flash memory.

    “Mythic does this in a 40nm process. Effectively, Mythic has turned back the clock on process scaling,” said Dave Fick, CTO of Mythic, in a blog. “While other system designers are struggling to bag from 7nm to 5nm, Mythic will breathe scaling to 28nm.”

    Mythic and others are using the technology to drive neural networks. In neural networks, a system crunches data and identifies patterns. It matches inevitable patterns and learns which of those attributes are important.

    A neural network consists of an input layer, a hidden layer, and an output layer. Data is fed into the input layer and then processed in the hidden layer with a set of coefficients. This either amplifies or dampens the input using a weighted system, “thereby assigning significance to inputs for the stint the algorithm is trying to learn,” according to AI startup Skymind.

    The problem is that the data exchange is sometimes gradual and consumes power. “To overcome this challenge, in-memory computing, where computing is done at the location of the data storage, has been proposed to accelerate the computation,” said Xiaoyu Sun, a Ph.D. student from Arizona situation University and lead author in a paper at IEDM. The paper was co-authored by the University of Notre Dame and the Georgia Institute of Technology. (Sun has transferred to Georgia Tech.)

    There are some limitations using existing memories, however. “The in-situ training accuracy suffers from unacceptable degradation due to undesired weight-update asymmetry/nonlinearity and limited bit precision,” Sun said.

    Instead of using existing memory, ASU, Notre Dame and Georgia Tech are exploring the exhaust of a 2T-1C ferroelectric FET (FeFET) reminiscence technology. “We propose a novel hybrid approach where they exhaust a modulated ‘volatile’ gate voltage of a FeFET to represent the least significant bits for symmetric/linear update during training only, and the exhaust of nonvolatile polarization states of the FeFET to hold the information of most significant bits for inference,” Sun said.

    Others are likewise working on the technology. For example, Leti is developing in-memory computing using RRAM, while Samsung is utilizing MRAM. It’s too soon to flaunt which technology will prevail.

    “You will bag different answers about the definition of in-memory computing, depending on who you ask,” Applied’s Lee said. “Although memory-centric computing is noiseless in the early stages, what is evident is how the traditional borders of reminiscence tasks are becoming blurred.”

    Another in-memory computing technology character is called neuromorphic computing. In simple terms, neuromorphic computing enables massively parallel analog computing for abysmal learning apps. “Neuromorphic reminiscence is more long term. The candidates are more enjoy ReRAM and modern memories, especially filament-type ReRAM. Other types of memories, including phase-change memory, can breathe used in neuromorphic computing,” Lee said.

    Chiplets maniaAdvanced packaging has been making gains in the market as an alternative to chip scaling. Different approaches possess been used in limited profile for decades in niche applications. Cost has been one of the main challenges here, but that could change as the industry marches toward heterogeneous integration, which involves putting multiple chips in an IC package.

    “An evolution in packaging technology is being driven by a slowdown of Moore’s law,” said Pieter Vandewalle, universal manager of the ICOS division at KLA-Tencor. “This is driving IC designers to work on both chip and package design to optimize the electrical and thermal behavior, and ultimately define the performance of the total package.”

    There are several ways to implement multi-die packages, such as 2.5D/3D and fan-out. In one example, Amkor and GlobalFoundries recently presented a paper on a 22nm FD-SOI device, which is housed in an advanced wafer-level package. The companies devised a test vehicle, and the goal was to study the chip-board interaction of the package.

    “Recently, wafer-level packaging has been in tall demand, especially in mobile device applications as a path to enable miniaturization while maintaining superb electrical performance,” said Jae Kyu Cho, a packaging engineer at GlobalFoundries, during a recent event. “The 22nm FD-SOI technology platform is an advanced silicon node for energy-efficient applications that deliver finFET-like performance. Combining both technologies will invent it more attractive for various markets, such as 5G mmWave, IoT, wearables and automotive.”

    The latest craze is chiplets. In chiplets, the thought of putting together different modules enjoy LEGOs has been talked about for years, but few possess implemented it.

    Fig. 3: Chiplets connected with interposer. Source: Georgia Tech

    Now, momentum is structure for chiplets for various apps. For example, there is a surge for compute-intensive specialized applications, such as machine learning. This is driving the need for domain-specific architectures enjoy hardware accelerators.

    Needless to say, these devices must breathe economically feasible to design and fabricate. That’s where chiplets fortunate in. “To meet current and future growth demands, providers need a more efficient approach to satisfy the needs of a wide ambit of data hub applications,” said Kevin O’Buckley, universal manager at Avera Semiconductor, the ASIC spin-off from GlobalFoundries.

    Chiplets are just one option on the table. Chip scaling and other approaches likewise remain in play. It’s likely that the industry will need more than one option.

    As before, it boils down to cost, performance and power. The industry is just genesis to sort out the issues. It will capture time before the dust settles.

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