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establishing a Reusable IP Platform within a gadget-on-Chip Design Framework focused against an educational R&D atmosphere | 000-541 test Questions and test dumps

by using Brendan Mullane and Ciaran MacNamee,Circuits and device analysis Centre (CSRC),school of Limerick, Limerick, ireland

summary:

A key problem facing the semiconductor industry is to mix highbrow Property (IP) from quite a few sources right away and effectively. Design times are consistently pressurized through time to market necessities and lengthening complexity. Industrial practices for developing system-on-Chip (SoC) IP have developed under these pressures, however making use of these practices in an academic ambiance gifts further challenges. The thought for constructing a framework for producing IP turned into in response to this reuse revolution and the benefits it brings to R&D. The capability to design high fine IP and to enable work practices for reuse methodology helps to obtain working SoCs in a timely and efficient method. This paper describes a technique for enforcing IP reuse practices applicable to an educational ambiance.

1. Introduction

a lot of elements are mandatory for efficient IP use, flexibility of integration, improved ease-of-use, minimized cost, and good work practices for developing IP. This paper is in response to exact work establishing an ASIC the use of 0.35ìm process expertise. The architecture in this IC is comparable to SoC designs that use an eight-bit CPU and linked peripherals. it's shown that the framework for IP development centered throughout this mission can be sure a hit deployment of each present and new designs in future tasks.

The current fashion in SoC design is to utilize latest IP as a great deal as feasible. IP within the variety of CPUs, DSPs and controllers, are being reused in new IC initiatives at semiconductor systems design residences. Engineering groups now design chips with thousands and thousands of gates in under a year. just recently, such productiveness would had been unimaginable, even unthinkable without hardware IP reuse. Most educational environments shouldn't have the supplies and infrastructure to permit such engineering capacity, although the underlying ideas of reuse can also be applied to allow more positive IP technology and abilities retention for advantageous R&D.

This paper introduces a collection of instructions and a technique used to be sure a constant approach to designing IP and to enable for reuse of these modules in future tasks. the first stage was to examine ideal industrial apply. Work describing the ASIC construction cycle and its impact on IP generation become carried out. a set of standards for guaranteeing IP great and ease of integration became additionally organized. A key aim became to ensure potential may be retained within the institution centre to have in mind expected graduate turnover.

2. IP Reuse Framework in CSRC

A evaluation of the regular considerations in design use and reuse was initiated [1]. a lot of IP specifications have been reviewed and these included Freescale’s Semiconductor Reuse regular [2], VSI Alliance’s set of specifications for setting up SoCs [3] and OpenMORE [4]. IP reuse could never have happened without necessities or without the underlying infrastructure [5]. Design and verification reuse, a truth of life these days for many SoC designs, ensures the productiveness gap is kept manageable[6]. Design reuse regarded an easy theory that can also be conveniently adopted, has persisted to be complex in practice. complications exist in getting engineers to trust that reusable IP will work anytime it's utilized in an IC. offering IP guide capabilities and adoption of a correct verification technique develops this trust.

2.1 SoC architecture and Infrastructure

The purpose of this task turned into to establish a design methodology for generating IP. The methodology involved architectural choices and choice of design-flows for IP construction accompanied by means of the prerequisite IC design equipment. venture criteria such because the SoC architecture, third-birthday celebration core use, in-condo IP construction and the system bus interface had been all regarded earlier than the IC architecture turned into concluded and the peripheral integration changed into conducted. The basic SoC architectural diagram is shown in determine 1 and the finished chip become taken via verification and the lower back-conclusion tiers of synthesis, design, static timing evaluation and remaining design rule checking.

determine 1: SoC Design structure

here key selections were made in relation to the IP aid structure.

2.1.1 Peripheral Bus Interface

The selection of a common SoC equipment bus for connecting the CPU to the system peripherals became vital to the targets of this assignment. using a standardized bus structure is elementary to setting up reusable IP. a lot of bus necessities were investigated for the wants of the CSRC IC tasks. The 8051 CPU became used during this design and despite the fact the inner special characteristic Register (SFR) bus turned into considered, the authors wished to employ a typical bus design to be reused in different IC implementations.

many of the essential IC and IP businesses base their IP portfolio building around a single SoC bus architecture. Semiconductor agencies comparable to ARM and LSI logic use the open source AMBATM [7] bus general. IBM makes use of its own proprietary CoreConnectTM [8] bus average. The OpenCores initiative makes use of the WishboneTM [9] defined bus interface. The authors followed that the AMBA bus structure changed into smartly supported amongst the IP seller group. This wide acceptance arises from the availability of an open bus ordinary this is license free and well confirmed in current SoC designs. purchasers have a excessive diploma of self belief picking IP it is considered vendor unbiased. moreover, the AMBA bus is well supported via EDA groups offering verification help. The AMBA bus was chosen as the bus interface for CSRC SoC tasks for these reasons.

The AMBA bus enables partitioning for modular designs[10]. Its methodology for embedded processor design encourages both a modular and first time appropriate system design. It additionally accelerates product migration by helping module reuse. In particular, the AMBA APB bus specifies a flexible interface and small overhead help for low bandwidth peripherals. The IP design using the AMBA interface is made easier by way of partitioning the excessive-conclusion and low-conclusion contraptions in the system and supports energy effective designs. all the peripherals during this design used the AMBA - superior Peripheral Bus (APB) as the standardized interface. The CPU as a single bus master become interfaced to all of the peripherals via an in-house designed AMBA bridge interface.

The benefits of using a typical bus interface for core construction are well documented [1, 10, 11]. A demo AMBA APB register module, shown in figure 2, become constructive for demonstrating the favored interface design to postgraduates. The RTL code for this module helped the crew to take into account the concepts of good coding apply to consist of parameterization and demonstrated the use of revision manage for code changes and worm fixes. the entire IP developed in this IC assignment may also be reused in another AMBA based SoC purposes and this aids future product and platform development

determine 2: pattern APB module

2.1.2 3rd birthday party Core Licensing

an extra big assignment turned into to designate an appropriate microcontroller for the assignment. The IP neighborhood was approached with reference to licensing of the CPU and debug cores. there have been a couple of points to licensing IP cores from an educational point of view. It became fundamental to be certain a licensing arrangement became made the usage of a non-industrial analysis- licensing mannequin. Many carriers had been handiest organized to license their cores based on a full business arrangement and the costs quoted had been past an educational analysis finances. Some providers had been willing to trust a decreased non-commercial license charge with the re-introduction of full prices supplied the IC proceeds to commercial software. other IP carriers confined their set of deliverables to FPGA netlist implementation only. This restricted their alternative of 3rd birthday celebration CPU and debug cores. happily, some IP agencies had event coping with academic situations and have been organized to free up IP deliverables and support for non-commercial analysis undertaking at a decreased can charge. The leading author changed into able to carry out a survey of correct cores and came to an agreement for the 3rd birthday party IP necessary for the SoC project.

2.1.3 Design Flows

The ASIC design circulation and electronic Design Automation (EDA) device alternative is a vital element of an effective IP framework. The choice of equipment must complement the design flows and assist reusability of IP. The centre accesses tool sets provided as tutorial programmes from the semiconductor EDA groups. The CSRC additionally has entry to standard EDA tools by means of the Europractice[12] software provider scheme. Their FPGA and Digital design flows have been drawn up around the availability of those equipment and to plan the SoC IP construction and integration. These flows were effective in picking out the distinct stages panic in the development of IP and SoC designs. in addition to the digital design circulation, a flow for FPGA prototyping was also brought. The FPGA construction enables for a reasonable design validation platform and adds self assurance by way of ensuring proper habits before closing tape-out.

2.1.three.1 Digital IC Design move

The digital design follows the traditional ASIC implementation route. a number of semiconductor company sites and technical paper searches revealed the general design circulate that exists for digital ASIC design [13], [14].

figure 3: Digital IC design flow

The design flow and equipment preference as drawn up in figure 3 were adapted to device availability and the alternative of IC methods supplied by means of Europractice.

2.1.3.2 FPGA Design stream

The FPGA stream in determine four is very comparable to the digital IC design flow, but the design equipment to put in force and software a FPGA design are different. The venture used the Xilinx design kits and equipment made purchasable by means of the Xilinx university Programme. They used Xilinx Spartan 2 and three boards to put into effect the digital design features. The Xilinx ISE webpack is a set of equipment that takes Verilog RTL code and runs it through synthesis, real layout to equipment configuration. The ultimate bit file can then be downloaded to program the FPGA gadget to examine the functional habits of the digital design. FPGA verification recommendations and their significance in design validation and reuse are discussed later.

determine four: FPGA Design circulation

2.2 CAD Infrastructure

The CAD infrastructure was more desirable to carry out SoC construction in the centre. The long-established constitution covered 3 low-grade UNIX servers for operating the IC design equipment and preserving undertaking facts. A plan turned into initiated to upgrade the IT hardware wants. every of the user PCs have been installed with VMware Linux, allowing clients to retain their windows OS but more importantly every notebook may use its personal CPU processing power with Linux to carry greater performance. Two excessive energy Linux mainframes, acquired for maintaining the mission databases have been also utilized as license servers for the supported EDA tools. the brand new set-up offers the efficiency necessities to perform IC R&D within the CSRC centre.

an additional step become choosing the EDA tools imperative for IP building. tools for verification and guaranteeing best of RTL code have been no longer in location. youngsters the usage of their Europractice membership, the centre had entry to general EDA equipment at a reduced cost. equipment equivalent to ModelSim for RTL verification and Leda for RTL evaluation had been obtained. The latest version of Design Compiler turned into additionally upgraded according to industry necessities.

three. Design Methodology and IP reuse Implementation

application of reuse can pay off in terms of construction cost and time-to-market. This part summarizes the development milestones for a regular IP design. Defining the movement and linked design stories helps guarantee a repeatable, high first-rate, and reusable block of peripheral IP. yet another benefit of a documented stream is that other design corporations can use this methodology to strengthen IP in an analogous way; ensuring IP is consistent in its implementation, integration circulate, deliverables, and overall high-quality.

3.1 construction Milestones

IP/SoC design milestones are important to the start of working silicon and reaching a ‘correct first time’ coverage. These milestones are markers positioned down all the way through the construction phase to control and measure the design undertaking and growth. These markers point out reviews taking place throughout the critical stages of the design section from beginning to end. Milestones take place on the herbal progression of the venture. determine 5 and desk 1 describe the sign-off milestones to consist of all fundamental design reviews.

figure 5: IP building Milestones

desk 1: IP building tiers

stageReview Description FSR functional Spec evaluation useful specification is comprehensive, details on effort estimation, work breakdown constitution and schedule. DSR Design birth evaluation Design beginning, practicing, RTL coding & synthesis checklistTPR verify Plan evaluate complete specification of verification ambiance, check situations, bus-models, transactors. RCR RTL Code evaluation RTL trojan horse fixes identified through exhaustive verification & RTL Lint/code checking TLR Trial design overview set up floorplan and function P&R. Floorplan in keeping with module connectivity, unravel congestion and timing –study clocking FVR final Verification review excessive precedence testing achieved. universal bugs within the RTL are fastened. coverage analyzed. Low precedence trying out adequate. FDR last Design evaluate evaluation integrity tests (DRC, LVS) STA, examine Vectors and ultimate gate-degree verification with comprehensive design timing.

3.2 project Database constitution

A standardized listing constitution is essential for IP reusability. an effective and simple to make use of database constitution ensures compatibility and consistency of peripheral design. IP construction includes specification, coding and verification as key design tiers. as a result, many support file codecs are required. IP preservation is also a key concept in IP reuse. The skill to log and hold music of design alterations is essential to the average exceptional of the design. determine 6 indicates the CSRC listing constitution to aid the IP construction tiers.

figure 6: common CSRC directory Database

3.three. Reuse instructions

three.three.1 Specification experiences

The design stories are significant when it comes to generating a framework for IP construction and reuse. These stories support documentation and confirm good design practices.

3.three.2 functional Specification

This doc offers an in depth useful description of the module and is written previous to the IP building. The FSR evaluate takes location to make sure all aspects of the peripheral functionality are covered. The specification will be used to delivery the design and RTL coding. The functional specification must be updated accordingly with any further aspects necessities. The CSRC makes use of a draft template document as a suggestion for producing useful block and IC design necessities.

three.three.three RTL Coding and analysis

RTL development contains coding the peripheral in a hardware description language equivalent to Verilog or VHDL. Verilog RTL become used and a group of coding guidelines for the IP technology became issued. This set of coding concepts ensures consistency, coding vogue nice and provides for more suitable renovation. The RCR is a excessive level assessment of the RTL code to make certain it's stylistically relevant and maintainable. The intent is to double-investigate the code satisfactory. The groundwork for this assessment is the RCR guidelines. RTL evaluation is conducted the usage of Leda for crosschecking RTL code suggestions in opposition t the Reuse Methodology guide (RMM). preliminary FPGA/IC synthesis can also be used to highlight any RTL concerns with reference to synthesis.

3.three.four Revision handle

Revision handle is critical to the idea of design reuse and ensures crucial information isn't lost all the way through the design section. Revision handle and file management is principally important during RTL coding as any code lost all over this stage can significantly affect the normal design timeline. To aid manage information, engineers use source manage management systems. These are usually bundled with the Linux operating programs or attainable from GNU (RCS, CVS, Subversion). These code management methods supply an entire heritage of each and every file as separate models.

3.three.5 malicious program protection

dealing with bugs is an important consideration for any design framework. it is usual to locate purposeful irregularities within the design and their occurrence does not replicate the skills of hardware designers. once an issue is recognized, it has to be resolved. All design groups need a method for tracking issues and making certain their decision. The authors proposed keeping a computer virus report for any design linked considerations.

3.four Verification and Validation ambiance

The verification phase is critical to delivering first time working silicon. Their verification methodology makes use of a twin tune method. Verification happens on the module level and additionally at the SoC device level. The Module Verification atmosphere (MVE) functionally validates the core and ensures all design characteristics were comprehensively verified. The SoC Verification environment (SVE) tests the cores’ habits at the equipment stage and in selected assessments the connectivity between the core interfaces. An FPGA/ASIC design verification method turned into used to validate the mission on the equipment SoC degree.

3.4.1 Module Verification atmosphere (MVE)

a necessary part of the MVE changed into the era of the APB Bus useful mannequin (BFM) to generate the useful conduct of the system bus. all the peripherals have been in response to this standardized bus architecture and this enabled the use of a widely wide-spread model to look at various the bus interface and registers contained within the peripherals. This mannequin extra provided a straightforward to make use of look at various atmosphere. The diagram in determine 7 illustrates this. The BFM utilized Verilog tasks for examine/write accesses, including wait state control and become reused in all the peripheral check environments. The BFM changed into helpful for working tests to obtain self assurance within the purposeful conduct and for concentrated on high code coverage.

determine 7: APB Bus practical mannequin

three.4.2 SoC Verification atmosphere (SVE)

The SVE consisted of a separate however an identical verify solution for FPGA prototyping and the ASIC gadget stage verification. The FPGA solution was constructive for mapping the complete SoC RTL code to consist of the CPU, debugger and all the peripherals onto a FPGA. figure 8 illustrates the fundamental structure carried out onto the FPGA gadget.

figure eight: FPGA Prototype Validation

The CPU and different leading peripherals are related together as a single platform and checks had been developed in R8051 CPU core program code to function the peripheral assessments. The ASIC verification ambiance is akin to the FPGA verify mattress, except in this case all checks had been run the usage of RTL and method selected gate-level stimulations. each of the peripheral firmware tests developed for the FPGA prototyping were reused at ASIC device stage.

4. outcomes and Conclusions

The project purpose become to put into effect a SoC design framework for the beginning of reusable IP. The chosen average gadget bus aided the building of plug and play peripherals that can be reused in lots of other SoC applications. The construction of the 8051 CPU external statistics bus to system bus-bridge supplied for a standardized interface and simplified the peripheral building.

The design flows of Figures four and 5 had been followed to be sure a constant design method for the building and equal help for industry ordinary EDA tools. The directory structure as explained in part 3.2 was also essential for associating files with each stage of the IC building and conserving a well-managed database. every of the implemented IP blocks follows this well-known database structure and this ensures reusability going forward. Design reviews ensured self belief and best of the IP block design. The Verilog code changed into reviewed to be certain revision control and RTL coding instructions had been adhered to. an identical review changed into performed to make sure the verification environments at module and gadget stage have been acceptable to examine the functionality of those designs. The RTL turned into validated on a FPGA equipment and checks were carried out at the gadget level to check the peripherals connected to the 8051 CPU.

The IP framework as mentioned during this paper is correct for implementation in an educational centre wishing to perform a reusable IP programme. this system and reuse concepts are favourite in trade, however because of funding and resource constraints, may additionally not all the time be handy to install in an academic ambiance. This paper discusses the implementation of IP building for decrease bandwidth peripherals; however the underlying concepts of IP use and reuse are the equal.

four.1 educational Centre Specifics

group of workers necessities for research are in the end resourced from graduates pursing MEng and PhD degrees. within the CSRC, workforce and educational researchers are liable for main initiatives and mentoring students. The graduates want knowledge construction to deliver them up to velocity and having a structured building methodology enables deliverables to be met in a well timed fashion. The merits of IP expertise retention became one more reason for introducing the IP construction framework, as work generated on tasks conducted in the past would were difficult to progress as soon as postgraduates had completed their analysis levels. This become an important problem to resolve, as constructive task work conducted during the past may additionally have been unnecessarily lost.

4.2. Future concepts

The cores can be further improved by means of presenting a gadget C or C model as part of the developmental stages to extra the level of abstraction and to speed up design verification and software construction.

SystemVerilog is a hardware design and verification language with superior points meant to aid users increase reusable, transaction-stage, coverage-pushed testbenches. techniques comparable to statement based mostly Verification (ABV) can be applied to the bus protocol to video display pin endeavor and the software of insurance-driven checks add self belief in working silicon and provide an exhaustive checking out atmosphere. These facets introduce ideas of verification reuse.

Design for check (DfT) is commonly excluded from the design circulate in an academic environment. DfT is a really crucial function obligatory for IP reuse. The IEEE 1500 standard for Embedded Core check (SECT) specifies a core wrapper design to accommodate DfT elements. This IEEE 1500 compliant wrapper design might deliver a positive extension to the latest IP building levels.

5. Acknowledgements

The authors acknowledge the support of the Circuits and systems research Centre (CSRC) in the electronic and computing device Engineering (ECE) Dept. on the university of Limerick.

6. References

[1] Australian Microelectronics community, "IP design and Re-use," Jun, 2005.

[2] Freescale Semiconductor, "Semiconductor Reuse regular v3.2," Feb, 2005.

[3] VSIA Alliance, "VSIA structure document v1.0," Mar, 1997.

[4] P. Bricard, Jean-Pierre Gukguen, "making use of the OpenMORE evaluation software for IP Cores," in ISQED 2000: Synopsys, Mentor pictures, March, 2000.

[5] J. Shandle, G. Martin, "Making embedded software reusable for SoCs," EETimes, Jan, 2002.

[6] J. Bergeron, "Writing Testbenches - functional Verificaton of HDL models", Kluwer tutorial Publishers, 2003.

[7] ARM, "AMBA™ Specification (Rev 2.0)," ARM LTD, might also 1999.

[8] IBM. CoreConnect Bus. architecture, "http://www-03.ibm.com/chips/items/coreconnect/."

[9] R. Herveille, "WISHBONE system-on-Chip (SoC) Interconnection structure for transportable IP Cores," OpenCores corporation, Sep, 2002.

[10] D. Flynn, "AMBA: Enabling Reusable On-Chip Designs," IEEE Micro, vol. 17, 1997.

[11] M. Kaskowitz, "bendy, standards-based IP key," EETimes, Dec, 2002.

[12] Europractice, "http://www.msc.rl.ac.uk/europractice,"

[13] QualCore good judgment, "QualCore SoC flow."

[14] V. P. Nelson, "VLSI/FPGA Design and check CAD tool movement in Mentor graphics," Feb 15, 2006.

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