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LPI 117-101 : Linux-General Linux, Part 1 Exam

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Test Number : 117-101
Test Name : Linux-General Linux, Part 1
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LPI cheat sheet

D32PRO, scalable & royalty free 32-bit CPU | 117-101 exam Questions and real Questions

by way of Digital Core Design

INTRODUCTION

* 32-bit, deeply embedded, royalty free

D32PRO is among the latest 32-bit CPUs attainable in the marketplace. It’s been designed by using Digital Core Design, IP Core issuer and SoC design condominium from Poland, accountable e.g. for the realm’s fastest or world’s smallest 8051 CPU. DCD launched greater than 70 different architectures for the reason that 1999, which were carried out in additional than 300 000 000 digital gadgets, that’s why you'll be able to be sure that rather considerable journey stands behind the D32PRO.

The D32PRO is a deeply embedded and royalties free 32-bit CPU. It’s a silicon confirmed answer (UMC 110nm, 1.2V, @150MHz, 128kB code), which consumes as little as 7µW/MHz (90LP procedure, minimal configuration) and a local of under 10.6 okay gates (0.029 mm2).

It’s been outfitted with Floating factor Coprocessor and a great range of peripherals like e.g. USB, Ethernet, I2C, SPI, UART, CAN, LIN, RTC, HDLC, wise Card etc. That’s why the D32PRO seem to be a pretty alternative for widely wide-spread ARM Cortex M0/M0+/M1/M3 and different 32-bit CPUs.

The D32PRO is wholly configurable, reckoning on task necessities, the IP Core’s measurement may also be significantly lowered. Then, superior vigour administration Unit makes the Core ultimate for embedded or IoT projects. then again, when mission requires the optimum computing power, then the efficiency will also be vastly elevated, even up to 1.48 DMIPS/MHz. That’s why the D32PRO is a commonplace 32-bit CPU, which will also be comfortably deployed each in Bluetooth Low energy, Wearables and cyber web of things undertaking. each IP Core has been organized by using DCD’s engineers in accordance to the valued clientele’ wants. So along with the D32PRO’s license, the customer receives silicon proven IP Core, which is ready to glue it with different SoC’s blocks.

elements

* variable pipeline, debugger, bootloader, gold standard code density

The D32PRO has been designed as a popular and completely configurable CPU, ipso facto appropriate for a superb variety of goal functions. It wouldn’t be possible devoid of long-established RISC architecture in line with DCD’s awareness. above all enhancements pioneered in world’s quickest 8051 had been exceptional for the D32PRO’s construction. amongst them, optimization of the maximal clock frequency to statistics route delays looks to be essentially the most giant. As an effect, DCD’s 32-bit CPU copes superb with many jumps within the code, but additionally (or reasonably, most of all) it executes easily homogeneous code, just like the arithmetic operations. All of that wouldn’t be viable devoid of variable pipelining architecture.

click to magnify

other innovations possible find in D32PRO’s guidelines’ set. It’s been based on special guidance which might be maximally congenial with the higher stage languages like e.g. C. As an effect came bigger code density and shorter instruction set. among them possible point out e.g.:

  • guidance which enable evaluation of both sign chains
  • discovering the primary one in the register.
  • as an example, they are able to take the FZB guide, which is liable for the optimization of the byte shopping. In general 8-bit CPUs the NULL sign shopping become in the type of all bytes iteration:

    within the 32-bit CPUs new optimization has been introduced – it allows for to check four bites within the register, at the equal time:

    however the real acceleration comes with the latest FZB guide, which has been carried out within the D32PRO. It makes it possible for to go looking the registry with only 1, single cycled guideline:

    The D32PRO has been fitted with 13 regularly occurring registers R0-R12 and most of them permit automatic refresh after interrupt return. because of it, the CPU tremendously hastens interrupts handling or context switching in real time systems. every of the outlined registers will also be used for arithmetic operations, which is especially useful if they examine classic 8051, where most effective ACC may well be used for that. Ipso facto, there’s no deserve to reload or store the content each time. The D32PRO has been additionally outfitted with configurable interrupt circuit, which enable 1 non-maskable interrupt and as much as 32 maskable interrupts. The pattern of interrupt detection is fully configurable, which makes it possible for the engineer to react on the side, on the degree and even to configure the interrupts priorities.

    up to date 32-bit microcontrollers may still be designed with the special situation for energy management. That’s why the D32PRO has been outfitted with the PMU, to handle the clock frequency dynamically. Ipso facto, DCD’s 32-bit CPU can drastically retailer the energy, when the maximal frequency isn't critical. additionally, the engineer can additionally configure the CPU’s clock divider and peripherals’ clock divider. So there’s nothing towards to enter best the CPU in a low vigor mode, when the entire peripherals will song the settings with the nominal clock. The CPU itself can be also entered into stop mode, when the clock is completely detached from the CPU and the return to commonplace mode can be released by an interrupt from any of the peripherals. The CPU can change-off unused peripherals, as neatly – which greatly reduces vigour consumption.

    And closing but now not least, they cannot neglect about the debugger and bootloader, that are engineer’s best friend during the IP Core implementation. DCD received adventure in 8051 hardware debuggers – the DoCDTM hardware debugger has been even awarded as EDN’s hot fabricated from 2013. So there’s no ask yourself then, than the D32PRO ought to be fitted with hardware debugger, which ensures full CPU handle from the Eclipse stage (finished gadget Eclipse, GCC => USB 2.0 cable => D32PRO). Unquestionable advantage of DCD’s hardware debugger is a reality, that it needs most effective two lines for verbal exchange, the place different options are in keeping with JTAG interface, which wants 5 pins typically. next, the bootloader allows for to store the firmware reminiscence program from the external FLASH reminiscence, linked through the SPI interface. And if it’s now not enough, one can add that D32PRO’s bootloader has been fitted with the hardware scrambler with the important thing stored in non-risky reminiscence, which efficaciously prevents firmware in opposition t reverse engineering.

    click to enlarge

    modern 32-BIT CPUs & THEIR effectivity

    * DMIPS/MHz vs hints & cheats

    There’s no secret that we’re all taking part in a race referred to as „electronics”: quicker, more advantageous, more savvy. It grew greater in fresh years, specifically if they seem at the datasheets with the benchmark outcomes. Even primary 8 bitters or 16-bit CPU present indecent/incomprehensible* efficiency (* sketch if unneeded). So there’s no wonder then, that the results equal to 2 or three DMIPS/MHz for 32-bit CPUs are further and further visible. however are they true? Is the CPU with e.g. 2.5 DMIPS/MHz as a lot potent as within the precise purposes? not critical…

    The D32PRO’s efficiency measured out with the Dhrystone benchmark is the same as 1.forty eight DMIPS/MHz. appears to be relatively decent as for the 32-bitter however… if they analyze different 32-bitters (let’s call them A, B, C), they are able to find in their facts sheets that they run:

  • CPU A: 1.fifty five DMIPS/MHz
  • CPU B: 1.77 DMIPS/MHz
  • CPU C: 2.eighty one DMIPS/MHz
  • So let’s dig deeper within the CPU A and what can they discover there? It will also be easily noticed, the prolonged variety of pipeline degrees, which enable higher efficiency for bound. but one may still remember that this can also be finished simplest if the code is homogeneous (e.g. arithmetic operations). but if jumps or interrupts might be introduced, the usual efficiency doesn’t look nearly as good. Of path you'll be able to always use prediction circuits or cache, but these would require more circuitry and in consequence might be physically bigger, can charge extra, and eat extra vigor. So it’s more desirable to be cautious after they see extraordinarily high Dhrystone consequences and the measurement of the CPU is enormously small (e.g. 1.fifty five DMIPS/MHz with 10k gates) bigger performance goes in hand with the larger CPU dimension and vice versa – smaller CPU denotes lower efficiency.

    however let’s go further and take a deeper seem to be into “CPU C”, where they are able to locate… 16, 24, 32 bit guidelines. So there’s no secret that if engineer would write 32-bit constant to the registry, he would need as a minimum two guidance. 24-bit guidelines complicate fetch command unit, which denotes bigger energy consumption and enviornment. So it’s superior to collate true performance (in precise functions) with the benchmark consequences offered in datasheets (carried out in accordance to larger, better, quicker indispensable).

    The utilization of prevalent compilers which help optimizations on the linking stage, completely vanish the conception of dhry21 benchmarks. as an instance they will take e.g. GCC for CPU A, CPU B or CPU C, where addition and multiplication have been completely removed from the ultimate code. not to mention, they all comprehend (don’t we?), that within the documentation for dhry21 has been strictly underlined, that the velocity for these operations influences DMIPS result. in addition, the existing exchange in dhry21 documentation has been pressured with the aid of too aggressive optimization, which they may see no longer long ago:

    As they can see from the above, 2.5-three DMIPS consequences, which may also be found in a considerable number of datasheets, have nothing in regular with the latest DMIPS specification. If they might use such variety of methodology, they may get for D32PRO 4 or even 6 DMIPS. but the place’s the sense?

    As we’ve outlined above, addition and multiplication were removed from the last effects. Why any individual would do so? reply is convenient, as a result of within the consequences with more than 2 DMIPS, the compiler optimizes DHRY code, working the addition and multiplication operations and putting the conclusion results as constants in the code. but the truth is diverse, as a result of within the precise DHRY and most of all – in the real purposes, multiplication is being held by using particular CPU’s directions. furthermore, function calls, in such organized verify, don't seem to be done, trigger the body of the feature has been placed directly from the leading loop (inline). one of these conduct eliminates name/RET guidance, which constantly take 2 or three cycles for each and every. Inline influences “additional optimization”, because a part of the operations “overlap” every different and is being stacked collectively. As a ultimate effect, they get much better DMIPS outcomes. The (now not) simplest query is that if such an artificial result can be utilized in a true life? answer to this question is somewhat glaring.

    summary

    * construct in peripherals vs entirely scalable?

    The D32PRO is a silicon proven, deeply embedded 32-bit CPU. It’s been designed as an IP Core tailored to the undertaking’s needs. It’s fully scalable, with Floating aspects (single precision IEEE-754 instructions) and fantastic variety of peripherals (with drivers) on board. DCD’s latest 32-bit CPU is a expertise independent IP Core, so it can be applied both in ASIC and FPGA. but the target expertise is ASIC, as the D32PRO is silicon confirmed (UMC 110nm, 1.2V, @150MHz, 128kB code). in addition, the IP Core is a royalty-free, so the complete answer is much more “cost pleasant”, trigger the licensee pays just one license charge after which is allowed to provide chips with none pay per chip. Digital Core Design presents free 3 months of comprehensive technical assist, which will also be freely prolonged under business situations.

    because it’s been said, the D32PRO is a time-honored and entirely scalable 32-bit CPU, so the target applications are countless. but when they would need to factor probably the most gigantic, they should still be:

  • IOT (cyber web of things)
  • smart Cities
  • smart Grid
  • BLE (Bluetooth Low energy)
  • clinical contraptions
  • Embedded Electronics
  • smart Electronics & Wearables and so forth.
  • however these are best the correct of the mountain…

    The D32PRO presents an engineer full configurability, it could possibly with ease swap-off some agencies of instructions, so the total are of CPU can also be significantly decreased. D32PRO can also change-off unused peripherals or however – he can use all of them, trigger the D32PRO comprises e.g. USB 2.0, Ethernet MAC, CAN, LIN, I2C, SP, CF & SD Card and so on.

    And if it’s nonetheless no longer sufficient, they can simply mention that the D32PRO can also be delivered along with comprehensive FPGA assessment board, which could significantly pace-up the checking out and validation.

    The D32PRO is an multi functional answer, so dare to assert greater…

    more information at www.dcd.pl

    in case you need to obtain a duplicate of this white paper, click right here


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