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Test Number : C9050-041
Test Name : Programming with IBM Enterprise PL/I
Vendor Name : IBM
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IBM tricks

The Tech hints That Make PCI-specific 6.0 And beyond possible | C9050-041 Free PDF and Free test PDF

Multiplying issues by using two and putting them on a roadmap is convenient, besides the fact that it does take a lot of braveness to do that. in fact making that 2X performance enhance ensue is, in lots of circumstances in the technology exchange, very difficult work. from time to time, it is seemingly impossible. This has been the case for peripheral buses in servers for decades, as an example.

however, at least according to the requisites for the next two velocity bumps on the PCI-categorical roadmap, issues are beginning to search for on the peripheral bandwidth entrance and a a good deal shorter two-year cadence is now possible, at the least for the subsequent a couple of years. in response to the difficulties in moving from a PCI-categorical three.0 spec to a PCI-express 4.0 spec, which took over seven years. They stay skeptical that beyond PCI-specific 6.0 issues will proceed to be exceptionally less difficult and would not be surprised to look the cadence slow – notably as probably the most tricks that make PCI-express 5.0 and 6.0 viable are variety of one-off hints. (extra on that in a minute.) And that ability greater one-off tricks ought to be invented. but they will say this. americans are damned clever, and that they did figure it out for PCI-categorical 6.0. So there is hope that the peripheral bus will hold doubling in bandwidth and not have its latency upward push, and therefore keep pace with compute and networking growth despite the fact that it can't necessarily capture it.

The time between spec preview, spec finalization, preliminary server deployments, and common server adoption is the rest however normal when it involves the PCI, PCI-X, and PCI-categorical buses. however suffice it to say that it is an elastic condition under the best of instances. From 2021 forward, based on the physics of wires and PHYs, this may beginning getting plenty harder to put in force. we're hopeful this is no longer the case and accept as true with that PCI-categorical 4.0 was an exception, no longer the rule, enabled with the aid of a well-known slow down in each peripheral and network ASICs – which have been definitely materials, clock pace, and encoding problems. They also strongly suspect that more than a number of server chip providers have been happy to just let adapter cards devour more lanes than are trying to make the lanes all go quicker. but as they stated lower back in October 2019 once they had been first discussing PCI-express 5.0 and 6.0 collectively, the usual server efficiency and Ethernet port bandwidth are radically outstripping the 16-lane PCI-specific bandwidth (shorthanded to x16 in the lingo), as this chart shows:

Admittedly, these are top bandwidths on all fronts, and never every device is designed with all add-ons running full out. And, that you would be able to always aggregate PCI-specific lanes and mixture Ethernet ports to increase a unit of bandwidth. So might be they will see x32 playing cards and even x64 playing cards at some factor, means fatter than the present x16 playing cards? Time will tell.

PCI-specific 5.0 turned into previewed in 2017, which turned into two years before the specification was set to be finalized in 2019 and around two years before it become expected to first appear in servers in 2021. The birth of the PCI-categorical 5.0 specification became handiest five months forward of the initial deployment of PCI-specific 4.0 peripheral controllers in servers, which debuted with IBM’s Power9 chips in its power AC922 servers used in the “Summit” and “Sierra” supercomputers developed for the U.S. department of power at its okayRidge country wide Laboratory and Lawrence Livermore country wide Laboratory, respectively. AMD added PCI-categorical 4.0 controllers to its “Rome” Epyc 7002 collection processors in August 2019, and Intel is not anticipated to guide PCI-specific 4.0 except 10 nanometer “Ice Lake” Xeon SP processors later this yr, but Intel is reasonably eager to get PCI-categorical 5.0 onto its Xeon SPs and is widely anticipated to carry it within the 10 nanometer “Sapphire Rapids” Xeon SPs launch someday in 2021 – and that's as a result of its Compute express link (CXL) shared memory protocol for accelerators – together with its personal GPUs and FPGAs – is dependent upon PCI-specific 5.0 protocol as a transport. Marvell’s “Triton” ThunderX3 Arm server processor coming later this yr will aid PCI-express 4.0 peripherals, and so will Ampere Computing’s “Quicksilver” Altra Arm server processor, also due later this year.

So, as that you may see, it takes a long time to head from spec intentions to spec birth to implementation. but possibly PCI-categorical 4.0 was the tail latency outlier. It could be a harbinger of doom when the clock and encoding and substances magic runs out. bear in mind, one hundred Gb/sec Ethernet and PCI-specific 4.0 each stalled, resulting in a tiny step of forty Gb/sec Ethernet and a protracted life for PCI-specific three.0. It took place as soon as, and their instinct says it might ensue once again.

The PCI-categorical 5.0 spec turned into mainly cooked this time remaining 12 months, and the difficulty shifted from design to engineering, with chip makers deciding the way to put in force this protocol in real products. The PCI-express 6.0 spec was at first previewed remaining year, and the Peripheral component Interconnect-particular interest neighborhood (PCI-SIG) physique that controls the spec is releasing greater assistance about precisely how the magic became performed to once once more double bandwidth and – get this – in reality in the reduction of latencies in comparison to PCI-specific 5.0 in some circumstances while at the same time including the ahead error correction (FEC) that the use of four-stage pulse amplitude modulation (PAM-4) encoding requires because it is a much noisier sign although it might probably raise twice as a whole lot information per signal as general non-zero return (NRZ) signaling regular in interconnects. The PCI-categorical 6.0 spec is still in development and is anticipated to be equipped by using 2021, and if historical past is any ebook, a 12 months or two later, depending on how aggressive server chip makers are, it is going to start performing in systems. There is no restrict to hungriness when it comes to peripheral bandwidth, and here's handiest going to get worse as PCI-specific is used to interconnect chiplets in a socket, sockets in a system, and peripherals either internal or outdoor of a system.

We certainly have the primary shape of what the PCI-SIG is trying to achieve with PCI-specific 6.0, which they noted final yr, but Debendra Das Sharma, and Intel Fellow and a board reminiscence for the PCI-SIG, hosted a webinar lately going over the nitty gritty particulars of the evolving PCI-specific 6.0 average and in a separate interview they did for subsequent Platform television this week, they talked a bit about how sustainable the two-12 months doubling cadence for the past two generations can be going into the longer term with PCI-specific 7.0, eight.0 and beyond.

The addition of PAM-4 encoding changed into a step forward in that it allows for for the doubling of the bits carried by a sign on the equal clock velocity for the device, conveniently doubling its statistics fee with out paying a clock pace and power penalty. This turned into now not simply indispensable for peripheral makers, but for server chip makers who had put anywhere from 48 to 128 lanes of PCI-express into their one-socket and two-socket processors already and they did not definitely have room so as to add more PCI-express controllers to double up the lanes for greater peripheral enlargement. but we're already taking a look at a future with 800 Gb/sec Ethernet, pushed with the aid of the hyperscalers and cloud builders, and they need ever-expanding PCI-specific bandwidth to do chiplet compute (assorted an identical units), hybrid compute (distinct architectures), and memory sharing (inside or throughout architectures) within a gadget, and that capability the PCI-SIG has to do anything. however can’t simply blow the doors off charges or energy, both.

Of route, nothing comes for free of charge, and as Das Sharma defined to us, the bit error cost for the signal going over the PAM-four encoding with PCI-categorical 6.0 become three orders of magnitude greater than for PCI-specific 5.0, which does not have PAM-four encoding, just the undeniable vanilla signal that contains one bit per signal. as a result of the high error price, that supposed that PCI-specific 6.0 would need to have ahead error correction.

The essential part of that chart above, as far as we're involved, is that the PCI-specific 6.0 spec required no greater than a ten nanosecond extra latency for transmits and receives relative to the PCI-specific 5.0 spec and that given the character of the peripherals – reminiscence class storage and accelerators with memories that are being made coherent over the PCI-categorical bus with CPU memory – the protocol couldn't take the a hundred nanosecond latency overhead that comes with ahead error correction the usage of PAM-four encoding on swap ASICs. in reality, it needed to be carried out in beneath 2 nanoseconds. (You heard that appropriate.) additionally critical changed into the requirement that the channel reach be the equal as with PCI-categorical 5.0 and with the equal highest variety of retimers, at two. (that you could see Das Sharma’s full presentation right here, incidentally.)

in fact, PCI-categorical 6.0 had to seem to be and feel like PCI-categorical 5.0 on steroids, however and not using a facet results.

The trick this time around became not to implement usual FEC, but a mix of movement handle unit (abbreviated FLIT for some unknown rationale) and cyclic redundancy assess (CRC) error detection that, when woven together in such a means that you best pay that a hundred nanosecond tax if whatever thing gets dropped on the bus and needs to really be resent. These bit mistakes, while extra a lot of because of PAM-four encoding, are nonetheless small sufficient that the general latency for facts transmissions is in reality anticipated to move down some from PCI-specific 5.0 to PCI-specific 6.0. (weird, isn’t it?) And in line with simulations with the current spec, Das Sharma says that the latency add with FEC plus CRC is between 1 nanosecond and a couple of nanoseconds, and this desk indicates the way it breaks down for baseline x1 and proper-conclusion x16 links, evaluating PCI-categorical 5.0 encoding with that of PCI-specific 6.0:

As that you would be able to see, the latency is bigger for smaller data packet sizes and for lower numbers of PCI-express aggregated lanes. because the lane counts go up and because the statistics chunks get greater the combination of PAM-4 encoding plus FLIT encoding layered on correct of it plus FEC and CRC error correction cuts the latency in half on x1 hyperlinks and on x16 links, too.

This. This. here is why they so admire engineers. So damned artful. And once they requested Das Sharma if the network ASIC business may gain knowledge of from PCI-specific 6.0 and undertake identical error correction, he didn’t say it was the stupidest factor he had ever heard.

if you provide a mouse a cookie, he needs a glass of milk, so they automatically desired to understand what Das Sharma concept the possibilities had been for carrying on with innovation within the PCI-express protocol, and chiefly on a two-12 months cadence. And they obtained a good engineer’s ever-hopeful answer, which is the lifeblood of the technology industry. (Getting pools of earnings and gains is relatively easy, but steady cleverness and proposal is difficult and deserves respect.)

“loads of this is dependent upon demand,” Das Sharma tells The next Platform. “If there's demand, they are able to get a hold of an answer. “if you had requested me when they did PCI-specific 3.0, once they did 128b/130b encoding, and also you requested me the equal query, i'd have said I don’t understand, i will cross that bridge after I get there. we're going to leverage PAM going ahead, absolutely, but is it going to be PAM-8? And we're undoubtedly within the realm of wild speculation, however maybe they will simply double the statistics rate. and then there are other things that they may do. for instance, they may go wider. As quickly as 6.0 is out, we're going to go and discover a bunch of things and have a collection of KPIs in entrance of us. And the greatest solutions are the ones that you've got basically no longer stated. And at the end, they will convey. There is not a question, and they have achieved it for six generations now.”

here's not hubris. it is real religion, and in a collaborative spirit at that. fresh right here in 2020, isn’t it?


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