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Test Number : C9530-001
Test Name : IBM Integration Bus v10.0 Solution Development
Vendor Name : IBM
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C9530-001 test Format | C9530-001 Course Contents | C9530-001 Course Outline | C9530-001 test Syllabus | C9530-001 test Objectives

Exam ID : C9530-001
Exam Name : IBM Integration Bus v10.0 Solution Development
Number of questions : 61
Number of questions to pass : 40
Time allowed : 90 mins
Status : Live

The solution developers should be able to construct message flows that use available transformation options such as Extended Structured Query Language (ESQL), Java, and the IBM Graphical Data Mapping editor and develop message flows that use various transport mechanisms such as JMS and web services. They should also be able to use capabilities to aggregate messages from multiple sources, control sequences in a flow, and use decision services. They are expected to build and use message models such as Data Format Description Language (DFDL) for non-XML data and to define and implement integration services such as database and WebSphere MQ services.

Section 1 - Integration Architecture and Design 6%
Explain the core architecture, components, and operating environment
Define IIB topologies

Section 2 - Installation and Configuration of IBM Integration Bus v10.0 8%
Install IBM Integration Bus runtime and toolkit
Validate the IIB environment
Define database resources
Define MQ resources
Define Web Services Resources (WSRR)

Section 3 - Development of IBM Integration Bus V9.0 Solutions 39%
Build integration solutions (application, service, and library)
Build a message model
Generate JavaScript client APIs from an existing integration service (high level)
Build solutions with basic built in nodes
Design and build transactional solutions with IBM Integration Bus
Build solutions with time schedules
Implement message transformations (graphical mapper, Java, ESQL and XSLT)
Build integration solutions with patterns (using built in patterns and creating basic patterns)
Build integration solutions with caching (Java, ESQL, mapping)
Build applications using routing patterns (decision, pub/sub, collector, point to point, fan out, request/reply)
Harden integration flows by handling exceptions

Section 4 - Extending IBM Integration Bus with Adapters and Other Products 8%
Integrate with JCA Adapters (high level)
Integrate with WebSphere Service Registry and Repository
Integrate with Visual Studio
Integrate with IBM Business Process Manager
Integrate with Operational Decision Manager

Section 5 - Application Assembly, Configuration and Deployment 13%
Demonstrate understanding of the relationship between the use of projects, applications, and libraries
Build and deploy applications using the Integration Toolkit and commands
Use keywords in deployment properties
Define and over-ride application properties using configurable services and user-defined properties
Describe and explain the Web administration console

Section 6 - Troubleshooting and Tuning 21%
Test message flow with flow exerciser
Use the debugger to locate and resolve problems
Configure and use trace nodes in a message flow
Configure and use user trace facility
Understand logging in integration solutions
Tune integration solutions with workload management and multi-threading
Configure and use Record & Replay
Gather and analyze message flow statistics and resource statistics

Section 7 - Security 5%
Describe and explain basic security
Use the PEP Node

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IBM Bus test

A PowerPC SOC IO Processor for RAID functions | C9530-001 Practice Questions and Study Guide

with the aid of Gérard Boudon, John Fakiris *, Thibaud Besson, Véronique Guerre, Pierre Debord, Jacques Rota-Biesdorf, Christophe Delapchier, Didier MalcavetIBM - 91105 Corbeil-Essonnes, France*AMCC - ePPC Division- Cary NC, united states


The Design of a PowerPC system-on-a-chip processor which integrates high speed state of the art 800 MHz PowerPC IP, DDRII-667 reminiscence controller, RAID assist common sense, and three PCI-X DDR266 interfaces with a prosperous mix of typical peripherals is described. The PowerPC, with on-chip L2 cache enabled, executes up to 1600 DMIPS. The RAID aid common sense is able to transferring 2 Gbytes/sec. The state of the art PowerPC, the excessive bandwidth information pipes, and the RAID aid logic make the SOC an important solution for RAID controller functions. energetic vigor consumption is as little as 6W with a 1.5 volt provide. The SOC has been applied in a 0.13 um, 1.5 V nominal-deliver, bulk CMOS system.


This PowerPC gadget-on-a-chip (SOC) design platform is intended to address the excessive-performance RAID market segment. The SOC uses IBM’s Core-join know-how [1] to combine a rich set of elements together with a DDRII-667 SDRAM controller, three PCI-X DDR266 interfaces, hardware accelerated XOR, I2O messaging, three DMA controllers, a 1Gb Ethernet port, a parallel peripheral Bus, three UARTs, everyday purpose IO, popular goal timers, and two IIC buses.

  • CMOS 0.13 um Copper
  • 7 tiers of steel
  • 11.757 million gates
  • Gate enviornment = 3x12 channels of 0.4um
  • Packaging
  • 29mm FC-PBGA (Flip chip Plastic Ball Grid Array)
  • 1mm pitch
  • 528 sign I/Os
  • 783 Pads
  • II- equipment OVERVIEW

    This SOC design consists of a high performance 32-bit RISC processor core, which is completely compliant with the PowerPC specification. The processor core for this design is based mostly upon an existing, fastened voltage PowerPC 440 core [2]. The core comprises a hardware multiply accumulate unit, static department prediction guide, and a 64-entry, entirely-associative translation seem to be aside buffer. The CPU pipeline is seven levels deep. Single cycle access, sixty four-manner set associative, 32- KByte instruction and information caches are related to the processor core.

    determine 1 SOC IOP processor block diagram

    A 2nd stage (L2) cache of 256 KB is built-in to enrich processor efficiency. functions that don't require L2 can also optionally use the L2 as on chip SRAM. The L2 memory arrays encompass redundant bits for parity and spares that can be related after examine and configured with on chip fuses.


    the key aspect of this SOC for top velocity information transfer is the significant 128b broad 167 MHz crossbar PLB (Processor local Bus) [1]. Two out of 11 masters can concurrently access one of the two PLB slave buses: one really good in high Bandwidth(HB) information switch and a 2nd one with Low Latency (LL). The same physical reminiscence in the SDRAM can also be accessed either on the HB or the LL slave bus through two aliased tackle stages. by way of convention (but now not required) the LL bus phase is used by means of the PowerPC to obtain low latency entry to reminiscence while the HB bus section is used by using the colossal facts movers such as the DMA engines. The Crossbar architecture separates the 64b address, 128b study records, and the 128b write information busses allowing concurrently duplex operations per grasp with two unbiased masters resulting in a top theoretical bandwidth of 10 Gbytes/sec.

    whereas the Crossbar arbiter supports 64 bit addressing, the PowerPC440 CPU is a 32 bit processor that can tackle up to 4 GB of genuine handle. The 64 entry TLB transforms this tackle to a true 36 bit PLB address (upper 28 bits are 0s) for 64GB access of the total tackle space.

    IV memory Controller / DDRII-667

    The integrated reminiscence controller supports each DDRI and DDRII SDRAM in sixty four-bit or 32-bit configurations with not obligatory ECC and is dual-ported with separate gadget interfaces to distinguish great of service. The Low Latency (LL) port implements smaller records buffers and is optimized for Low Latency entry while the high Bandwidth (HB) port has larger statistics buffers and is optimized for maximum throughput. memory accesses during the LL phase can also optionally be programmed to have higher precedence than these of the HB phase, with no trouble enabling the LL requests to move forward of HB requests within the reminiscence examine/write queue.

    determine 2: reminiscence Controller Queue block diagram

    computerized self-refresh entry is supplied to help RAID battery-backed caches. in the experience reset is asserted the memory is instantly placed in self-refresh to maintain the memory contents. energy may be faraway from the SOC so long as the reminiscence is presented vigor from an alternative supply. The memory is saved in self-refresh except particularly steered to come back out of self-refresh by way of the PowerPC.

    DDR I and DDR II SDRAM are supported via a versatile, completely programmable timing interface. apart from programmable command and interface timings, the memory controller supports a nice grained, part improve/delay mechanism to enable Clock/records/DQS and DM interface timing adjustment and contains a digital DLL to permit system, voltage, and temperature compensation. the following table lists the supported DDR1 and DDR2 facets:

    DDRII SDRAM DDRI SDRAM Clock Freq 200/266/333MHz one hundred/133/166/200MHz CMD Timing Programmable Programmable Init. sequenceProgrammable Programmable Interface Width 32/forty-bit 64/72-bit 32/forty-bit sixty four/seventy two-bit forty-bit ECC SEC/DED per word SEC/DED per be aware 72-bit ECC SEC/DED per DWord SEC/DED per DWord Burst duration4 4 data Strobe Differential/Single Ended Single Ended give Voltage 1.8V 2.5V O Interface SSTL_18 SSTL_2 New functions - ODT (On Die Termination)- OCD (Off-Chip Driver) calibration- Posted CAS- AL (Additive Latency)    

    V - Hardware XOR

    The Hardware XOR engine computes a bit-clever XOR on up to 16 information streams with the consequences saved in a chosen target. The XOR engine is driven by means of a linked record Command Block structure specifying manage tips, supply operands, goal operand, fame advice, and next link. source and target can reside any place in PLB and/or PCI tackle space.

    VI - I2O Messaging

    The I2O messaging unit provides 2 messaging queues (i.e. 4 FIFOs) akin to what is defined within the I2O version 1.5 specification. apart from the functions defined by using the common, the I2O messaging unit provides hardware to immediately circulation a message from the host to the SOC as a result of a messaging queue update devoid of PowerPC involvement and helps sixty four bit message frame addressing.

    VII - DMA Engines (2)

    the 2 DMA engines are high efficiency statistics movers pressure via Command Block constructions. each and every DMA engine can independently do supply to goal facts circulate, supply to two goal information move, target pattern fill, supply pattern determine, target LFSR fill, and source LFSR verify. supply and target can reside any place in PLB and/or PCI address area and have any byte alignment

    VIII - PCI-X DDR 267

    ordinary PCI is a multidrop category of bus which limits its efficiency. The PCI-X DDR 267 mode 2 [5] is an evolution to some extent to point bus whereas holding compliance with legacy PCI. The PCI-X 267 mode 2 introduces a DDR scheme to double the performance to as much as 2 Gbytes/sec for a sixty four bit bus.

    among the new features of the PCI-X mode 2 are DDR, ECC, and OCD control. The circuit of figure 3 that controls the impedance of the Off chip driver is in accordance with the comparison of a bunch of NFETs in parallel with an exterior calibration resistance in a primary step. The adjustment is performed by using turning on/off a few NFETs. In a 2d step when NFETs are calibrated, the PFET impedance is compared to the NFET which may still be equal to the exterior Resistance. The influence of On/off PFET/NFET is utilized to the final FET’s of the Off chip driver.

    figure 3: OCD Off-Chip Driver manage circuit for PCI-X DDR mode 2

    Miscellaneous Peripherals

    The SOC includes all the average peripherals required for a RAID controller together with a 1Gb Ethernet port, a eighty three MHz parallel peripheral Bus (as much as three contraptions), three UARTs, common purpose IO, conventional aim timers, and two four hundred KHz grasp/slave competent IIC buses


    The mixture of various cores equivalent to a 800MHz CPU, three PCI-X DDR266 and a DDRII-667 SDRAM controller on a single SOC ends up in the implementation of five (5) PLLs.

    To generate the multiple excessive frequency clocks required by way of the SOC, two PLLs were cascaded to generate the CPU, reminiscence Controller, and peripheral clocks. The CPU PLL drives the CPU and connected peripherals whereas the DDR PLL is used exclusively to generate the 1X and 2X clocks for the memory controller. memory and CPU are synchronous and the clocking is constructed from the same exterior low frequency device clock. The DDR PLL enter is pushed via the PLB clock (generated by the CPU PLL).

    To cut the cumulative skew effects of non-adjoining cascaded PLLs the comments of the DDR PLL is at the end of the clock tree it drives, conveniently eliminating the prolong of its input clock from the CPU PLL. This scheme can support the 2 PLL’s in every nook of the die internal their respective cores.

    There are three independent PCI clocks inputs, one for each and every PCI-X interfaces with a PLL that generates a 2X inside PCI clock for the DDR mode. The PCI CLock domains and the PLB clock area are absolutely asynchronous. A Request/renowned handshake protocol became favourite to a two ranges - double latch - synchronizer simplest answer for records switch between PLB bus and external PCI agents. This design strategy eliminates hazard and minimized latch metastability complications.

    X - vigor DISSIPATION

    The PowerPC structure is neatly reputed for its low energy dissipation coupled with high performance.

    figure four: power dissipation breakdown

    The vigor breakdown of the numerous cores on the chip highlights the turning out to be importance of the reminiscence controller and PCI-X busses at excessive frequency.


    determine 5: Chip design displaying I/O circuits - PLL and DLL’s, all SRAMs

    as a result of the significant number of I/O (783) needed to combine the entire peripherals, the I/Os are placed in an area array across the die. A peripheral method for IO implementation turned into feasible with a staggered structure; despite the fact, it would have resulted in a larger die size, and a greater noise sensitive part as a result of significant simultaneous switching.

    The machine is based on an ASIC with integrated synthesizable cores - additionally named IP’s - apart from the PowerPC CPU core which is a precharacterized tough core with optimized timing analysis and tuned clock distribution to achieve 800MHz. through evaluation the identical CPU core runs only at 600MHz if implemented as a soft core with the most advantageous optimization equipment.

    good judgment is described in Verilog and synthesis performed with Synopsys synthesis device. The physical design together with floorplaning, placement and wiring become carried out with IBM’s proprietary Chip Bench tool. special care became taken in physical implementation for minimization of noise brought about with the aid of coupling and simultaneous switching on suitable of the generic sign integrity verification.

    wide simulation of each and every core with simulation after SOC integration has resulted in a first circulate decent product.

    XII- verify outcomes

    a special board with modular strategy for PCI-X, DIMMS, and peripheral attachments has been developed. It enables the debug of the SOC device with DDR1 and DDR2 SDRAM as well as PCI, PCI-X and PCI-X DDR connectors. Debug was done with the Riscwatch debugger in the course of the JTAG serial hyperlink I/O.

    determine 6: Board used for debug with DDR2 DIMMS near the IOP processor and PCI-X bus analyzer


    A SOC integrating a PowerPC CPU core with a big number of state of the art and traditional peripherals has been designed and Tested respectable on its first pass of silicon. The CPU has been confirmed at 667Mhz and leading interfaces similar to DDRII SDRAM at 667MHz and PCI-X DDR mode 2 at 266MHz.


    [1] IBM Corp. (1999) Coreconnect Bus architecture, Hopewell Junction, the big apple. [Online]. accessible:

    [2] IBM Corp.. (2000) PowerPC Embedded Cores, Hopewell Junction, big apple. [Online]. obtainable:

    [3] JEDEC ordinary DDR2 SDRAM SPECIFICATION (Revision of JESD79-2) January 2004

    [4]W.Lau “Overcoming DDR-2 interface challenges” EDN, Jan 22, 2004

    [5] PCI-X Addendum to the PCI local Bus Specification, edition 2.0

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