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EMC E20-624 : VMAX Family Specialist test for Platform Engineers Exam

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Test Number : E20-624
Test Name : VMAX Family Specialist test for Platform Engineers
Vendor Name : EMC
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E20-624 test Format | E20-624 Course Contents | E20-624 Course Outline | E20-624 test Syllabus | E20-624 test Objectives


Exam Title : Dell EMC Certified Specialist - Platform Engineer - VMAX Family (DECS-PE)
Exam ID : E20-624
Exam Duration : 90 mins
Questions in test : 60
Passing Score : 63%
Official Training : VMAX Family Installation and Maintenance (MR-7CP-VMAXIM)
Exam Center : Pearson VUE
Real Questions : Dell EMC VMAX Family Specialist Real Questions
VCE practice exam : Dell EMC E20-624 Certification VCE Practice Test

Symmetrix Hardware: VMAX 1/2 series 12%
- Identify the VMAX 1/2 series platforms and their differences
- Describe the available VMAX 1/2 series configurations
- Explain the VMAX 1/2 series hardware architecture
- Describe the VMAX 1/2 series System Bay components
- Describe the VMAX 1/2 series Storage Bay components

VMAX3 Fundamentals and Hardware 24%
- Identify the VMAX3 series platforms and their differences
- Describe the available VMAX3 series configurations
- Explain the VMAX3 series hardware architecture
- Describe the VMAX3 series System Bay components

VMAX3 Local and Remote Replication Fundamentals 14%
- Explain VMAX3 local replication requirements
- Identify TimeFinder SnapVX features, capabilities, and TimeFinder management options
- Describe VMAX3 SRDF remote replication business requirements and product use cases Describe VMAX3 SRDF architecture, features, capabilities, management, and VMAX Open Replicator

VMAX Family Installation and Maintenance 50%
- Install and Maintain VMAX 10K, 20K, and 40K
- Install and Maintain VMAX 100K, 200K, and 400K



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EMC Practice Questions

creating more suitable fashions For application And Hardware Verification | E20-624 test questions and PDF Download

Semiconductor Engineering sat down to talk about what’s ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep researching analysis at Nvidia; Nasr Ullah, senior director of performance structure at SiFive. What follows are excerpts of that dialog. half considered one of this dialog can be found right here. part two is here.

SE: We’ve been closely reliant on models in the past. do they get by means of with those identical forms of fashions in the future, or will they need to birth rethinking every thing?

Garibay: For chiplets, all and sundry must be on the identical page. all of them have to be interoperable. within the industry, I’m no longer aware about any service provider product that has silicon from different carriers in a single chiplet-ish type of package, aside from HBM memory. It’s kind of a company concern. We’ve under no circumstances solved the problem of what occurs if the integrated equipment fails and who pays for it. the inability of some form of sign-off is an opportunity for the interconnect IP companies and the EDA businesses to step in and turn into some type of honest broker and say, ‘ok, I’ll log your interface, validate some VIP for it as a provider, and have that obtainable for other corporations.’ So there’s an opportunity for a 3rd birthday celebration who’s capable of validate these two issues should still work collectively. The whole liability challenge is what has definitely limited the marketplace for chiplets up earlier. I’ve tried thrice to get something like this off the floor and check with different businesses. every person’s excited until the company guys and lawyers get concerned and say, ‘well, how can you clear up this?’ That’s a real problem. Popping it up a degree, where they get to the models, they ought to figure out a way to outline these fashions within the same way they have for generations. There’s doubtless a big opening here for formal verification, to be able to say all these chiplet interfaces should be formally verifiable. and some EDA enterprise that’s doing formal can step in and say, ‘Yep, we, here it's.’

Ullah: I’m a big fan of emulation. besides the fact that children, remains too costly. It expenses a whole bunch of thousands of dollars. They made a lot of development in a old business, where they needed to build Android software and run a bunch of applications — including including stuff with Java on them — to make sure things were working. That’s an in depth volume of application, and it is awfully tough to try this on a basically useful foundation. So i used to be a huge fan of having both a purposeful model or a efficiency model in a hybrid state of affairs, and they used Mentor’s emulation platform and have been very successful with RTL that was coming from a forte chip, and then worked with a 3rd birthday party to be sure an OS received booted — Linux or Android. after which they labored on getting the application operating. That turned into very a success for efficiency, vigour and functionality. They deserve to leverage that sort of hybrid model much more, the place they will focus on useful performance, RTL, and mix and suit of these things. but no longer each company can manage to pay for to purchase an emulator and set all this up. So if the organizations can work out some system like Amazon does, the place that you would be able to get time on emulator to put your device in and blend it up along with your utility, that is where they should go for the longer term.

Godil: Emulation was this sort of game changer when it got here to verification methodology. Having the capacity to make use of your software suite as a trying out platform was effective, specifically when they constructed further and further advanced chips. That has a captivating tie-in with models as they build new chips with new functionalities. Being capable of leverage the software for them is primary. The utility crew should go Strengthen their software, so that as soon as your hardware is in a position, they've the software able to go. There’s this type of dependency, and one way to get rid of that depenency is to provide the utility crew with greater-stage fashions, on which they can boost their application. There are distinct ranges of fashions. practical fashions might also have lots of details, however the utility team doesn’t need that type of fidelity. There are lower fidelity models which are a lot faster, and the application group can do all of their building on those. We’re going to see extra of that to allow utility to shift left, in order as soon as they are able to get it on the emulator platform they can run the software and have that able to target new elements.

SE: What’s diverse about these fashions?

Godil: each mannequin that you just build has a huge cost to it. somebody has to head build it, after which you ought to hold it, so that you must be very cautious in finding out what the price is and buying and selling that off with the cost. there is lots of price in establishing more moderen fashions that may pull in application, and we’re going to see greater of that as they go ahead. As you construct further and further hardware facets that need targeted utility, the utility teams are going to want some variety of platform for his or her construction earlier than the design is equipped. practical fashions take too lengthy every now and then, certainly high-fidelity practical fashions. There are lots of alterations, so that you can’t basically build the functional models too a long way ahead of the designs. There are all these code development points. however the application team doesn’t in fact care about all these details. They need a better-stage, in case you will — an ISA simulator, in case you’re considering processors. you've got these ISA simulators which are developed very early on that don’t have any of the microarchitecture details or a lot of the purposeful particulars that the the different groups care about. You’re going to look that for the SoC as neatly. We’re going to borrow these ideas for processor building, and you'll follow it to different different hardware designs, as well.

Ullah: For models from processor work, I agree they need a high-degree ISA mannequin for utility development. They additionally need a better-constancy purposeful model for doing verification greater accurately, and they want a low-constancy cycle-approximate mannequin, maybe useful with desk-based timing, after which a high-constancy efficiency model, cycle-approximate mannequin, to do microarchitecture work. after which these should be able to tie to RTL or SystemC, or other fashions, in a hybrid fashion.

Godil: What I’m arguing for is a low-constancy fast mannequin, like the ISA simulator, however for the relaxation of the design. That’s what’s missing at the moment. So an awful lot of their hardware designs are actually exposing things to application, and the application team actually needs anything to be capable of go goal those facets. Simulators are not new. They know be aware of how to construct them. What they don’t have is that type of an abstraction-stage mannequin obtainable for the relaxation of their hardware chips. We’re going to see further and further of that as you are attempting to tug within the software for trying out.

Schostak: one of the vital things formal forces individuals to do is believe more about how to definitely define interfaces and every thing else. With simulation and emulation, it’s too effortless to assert, ‘This RTL is decent sufficient. I’m now going to run some tests and spot whether it works. If it works, that’s best.’ I’m no longer asserting that’s usual practice. however’s a extremely handy trap to fall into, whereas the formal tool is truly going to tell you if there’s things that aren’t wholly tied down to your requirements. That gives an outstanding chance for the well-described interfaces to communicate across boundaries on the model inner. We’ve pointed out time to market. You’re bringing forward the RTL schedules. and then, the window you’ve got by which to build the model whereas it’s nevertheless valuable is shrinking down because you haven’t received RTL that can run in an emulator. If I’ve acquired a high-degree specification of what I’m going to build, what am i able to in reality generate from a excessive-stage specification that may be able to generate some points of my ISA mannequin? so that it will supply that person a head beginning, as smartly.

Garibay: a lot of what everyone is speakme about is terribly processor- or SoC-centric. In AI chips they now have a C mannequin. however with the intention to do a full photo analysis, one graphic and a C mannequin takes teraOps. That’s one of the vital motives I consider that the verification of proper AI chips is different and slightly extra challenging. in case you’re going to be verifying at a stage where you’re exposing each multiply and each add, the number of operations is so big that, in Verilog, they are able to’t even do an one picture in an inexpensive amount of time. so that you’re reduced to announcing, ‘ok, let me get this nook.’ devoid of an emulator, we’d be useless. They couldn’t, couldn’t advance their compiler.

SE: in the past, when they have been setting up advanced-node chips, they mostly were going into consumer instruments or servers. one of the crucial most superior designs now are being accomplished for automotive and robotics, and they’re alleged to work for more than a decade. What can also be accomplished from a verification standpoint to make this viable? Is verification shifting left and correct?

Garibay: safety and protection historically have been perceived more as structure, and then structure defines assessments that will also be used to examine them. I’m no longer excited about using round or driving cars that are in line with 5nm. The purposeful protection facet of here is tremendous exciting. It basically forces a decomposition. You have to ruin everything all the way down to, ‘this is the protected part, this part isn't secure, and here is the interface between them. here's how I choose those things.’ and then for AI, there is not any practical safety definition. How do you judge whatever thing it really is seventy two% accurate as functionally protected? Some vendors are imposing a scheme the place they have a processor from enterprise A and a processor enterprise B, you run them both in parallel and also you vote one off. It’s like avionics, where you have a balloting gadget among three results. here's a major, large open space, and it’s no longer clear how they even structure these complications such that they're verifiable, or amenable to ideas for verification. And it’s constraining how they circulate ahead with it.

Godil: if you work in the ISO 26262 standard, one element that becomes obvious definitely straight away is the deserve to doc every single step of your verification circulate. anytime I hear documentation I believe of overhead. It’s greater forms that engineers ought to deal with. however my hope is that they will build equipment get rid of that overhead, and i’m in reality just a little effective about it. The extra they put money into documenting, the extra it will support with the different aspect, where they need to instrument their strategies to get the records so they can feed it into and train clever programs. Formalizing their approaches and documenting each step that they do will take us step in that course. I view functional protection as helping with that effort. It aligns neatly with the wants for each issues. however they do need improved equipment to support dispose of lots of the overhead that these those practical security flows imposed on the teams.

Schostak: With purposeful safety and protection, there's that documentation overhead. If a trojan horse escapes out into the field, that you could’t basically fix the hardware. The hardware already may have long past during the certification manner to be functionally secure, and so on., and that takes years to go through. so that you can’t depend on bugs being present in field. It’s now not like you can re-spin it and fix it inside a year. It’s no longer that elementary. it is going to nevertheless require a number of years of analysis to find the hardware and the application that runs on it. That forces a better stage of assurance that there isn’t anything else that goes to affect practical protection-critical or protection-crucial methods, which are often average things like ECC or redundant gadgets.

Ullah: Getting enhanced tools is crucial, but really it depends upon checking out, trying out, testing. I labored on the Motorola chance at 88100, which changed into within the nostril cone of a Patriot missile, and each time a Patriot missile ignored a Scud during the Iraq warfare I questioned if it changed into some application I wrote. The F18 had an 88110 from Motorola, too. When an F18 crashed, they had to determine why. The trigger become a nested interrupt controller. I needed to debug that.

Rajendran: one of the vital challenges they didn’t focus on from a tool aspect of view is that they're all evolving with ISA requirements, and there are new things being added. however from a company element of view, the firm itself isn’t there. They don’t have frameworks and different cases in vicinity, so if a bug is discovered on a product 15 years from now, they can't simulate it and say here is a malicious program. There isn't any methodology in region. can i still use Synopsys or Cadence tools that I used 15 years ago? Will it nevertheless be supported if I actually have considerations? those are unanswered questions. And for all of the verification that I did, now I have to continue information for 15 years. So there are data explosions inside businesses. Some companies are thinking ahead and searching into it, however others are still clueless at this aspect. They’re focusing on the design part of it, but they’re no longer what they’re going to do if a chip comes again.


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