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IBM Modeler Test Prep

assisting hardware assisted verification with synthesizable assertions | SPS-201 test Braindumps and Free test PDF

Marcin Kubica, The school of Bielsko-Biala (ATH) Włodzimierz Wrona, Evatronix SA, Bielsko-Biała Wojciech Sakowski, Silesian college of expertise

INTRODUCTION

The ever starting to be complexity of programs-on-a-chip requires more and more subtle strategies of their design and verification. The important profit in SoC design efficiency resulted from vast adoption of design reuse of complete useful blocks (IP cores).

Verification methods utilized throughout SoC integration section focus on the correctness of the combination of numerous IP cores and on interplay of hardware and utility because the latter implements now big a part of the goal software functionality. Simulation of the whole SoC on the register transfer stage turns into excessively time drinking due to its complexity. To take care of this designer use virtual structures, hardware emulation and /or prototyping.

digital systems are constructed as collection of transaction stage models of IP cores in addition to guide set simulators of the CPUs, DSPs and MCUs that are a part of the SoC. Accuracy of such illustration is good ample to simulate software/hardware interplay and statistics transfers that happen all over SoC operation whereas they summary many details represented in the RTL code and hence they present a lot bigger simulation speeds.

Hardware emulation nonetheless allows for execution of the utility on the real synthesized hardware of the total SoC, implemented constantly in assorted FPGAs and extended with debug helping instrumentation.

functional correctness of the IP cores being built-in may still be ensured earlier than the SOC integration part and is an enormous duty of the IP core enterprise.

In most cases verification of the IP cores is finished totally through application simulation of its RTL mannequin. This paper items benefits of hardware assisted simulation and use of synthesized assertions for boosting verification method of IP cores.

VERIFICATION OF THE JPEG 2000 ENCODER IP CORE

Over pretty much two a long time of its existence the semiconductor industry developed a couple of verification and first-rate assurance strategies that outcome in respectable products that can be with no trouble integrated into SoCs.

Simulation on the RTL level has been the leading system of verification and it nevertheless is probably the most vital one. youngsters, it is terribly tricky to base the verification of definite classes of cores on simulation because of the undeniable fact that complexity of computations carried out by the core, range of the core configurations and variety of records units to be used in the testing technique outcome in excessive simulation time.

In such case hardware assisted verification is a need to and availability of hardware atmosphere that accelerates the examine execution and at the same time gives least expensive debugging capabilities is awfully useful.

This turned into the case of Evatronix JPEG 2000 encoder core.

The hardware platform they developed enabled the enhance of speed of the verify execution up to 300 times.

HARDWARE PLATFORM FOR IP CORE VERIFICATION aid

For the aim of positive acceleration of testing of IP cores that are computation intensive and that generate excessive simulation time a hardware prototyping environment has been developed (it's called EB7E).

Its most important talents is capability of interplay with the testbench that runs on the host computing device. real connection is realized with PCI categorical hyperlink. They developed the application that implements SCE-MI interface (commonplace Co-Emulation Modeling Interface [6]) between the transaction level testbench written in SystemC that runs on the host computer and the design-under-check (DUT) carried out in the EB7E board. The developed infrastructure makes it possible for alternative of the utility transactors that permit interfacing of SystemC-based mostly TLM testbench with the RTL code of the core all the way through application simulation with SCE-MI transactors that link this testbench to DUT within the prototyping board.

The board is able to emulate/prototype designs with complexity as much as 2 million ASIC gates. this is more than most of individual blocks used in existing SoC designs and therefore a whole lot of space is purchasable for instrumentation improving the debugging process realized by way of ability of this prototyping board.

therefore they decided to apply the idea of synthesizable assertions to further increase effectiveness of hardware assisted verification technique of IP cores.

SYNTHESIZABLE ASSERTIONS

Property checking has been used for fairly ages in application construction. VHDL fact commentary was supposed to provide opportunity of hardware property checking all over simulation time. It turned into however very confined in its expressive energy. in the late ninety’s and first years of this century languages like “e”, Sugar (that changed into later transformed into PSL commonplace and eventually integrated into VHDL) and SVA – a subset of SystemVerilog – had been defined to present designers concise syntax in a position to outline complicated houses. Over closing decade assertion primarily based verification and fact based mostly design became broadly adopted [1].

First and nevertheless doubtless widest use of assertions became definition of information alternate protocols on the boundaries of useful blocks, especially connected via average on-chip buses (like AMBA) or off-chip serial interfaces (like USB or PICe). despite the fact over time embedding the assertions in the RTL code grew to be a standard observe that cuts down debugging time by using producing messages of fact violations and dashing up identification of the error vicinity. assertion insurance grew to become one of the crucial verification quality metrics and formal verification provides ability to verify them against RTL code in a static manner enabling error detection earlier than simulation starts.

regrettably, average synthesis tools do not aid synthesizing assertions at once. Assertions embedded in the RTL code are quite simply not noted, fact based displays found outdoor RTL aren't supposed for synthesis. therefore – with commonplace set of design tools taking competencies of assertions all over hardware assisted verification is inconceivable.

So inventing how to convert assertions into the hardware that could be positioned along with the synthesized RTL into prototyping platform became recently a field of research. Taking proposal from [2][3] authors has increase the device to take care of this difficulty. PSL code is first parsed and the internal representation that will also be described with definite graph is created. Then this graph is processed to produce RTL code that can be embedded with the RTL code of design-beneath-verification (DUT).

Hardware assertion configures an FPGA half constitution into a circuit which is known as Hardware Checker (HC) and is responsible for trying out a given property [2]. Hardware Checker generates error sign which may well be propagated out of the FPGA structure during which prototyping or emulation takes vicinity and may be then linked to the relevant fact within the supply code of the given module. This enables the clothier to music down the real cause of inaccurate habits captured in hardware to be found in the simulator environment which provides tons greater observability of the design.

for this reason simulation runs of useful checks are restrained to these situations wherein problems turn up and synthesizable assertions supply an further comments making identification of the error places more convenient.

instance 1

Hardware implementation of an statement is illustrated in the following instance. This proces is in line with the MBAC algorithm described in [3].

PSL (Property Specification Language [1]) source code for the fact is awfully fundamental:

assert a ; b

Semantics linked to this kind of code is as follows. statement acknowledges incidence of the sequence “a” and next (after this occurs) identifies the sequence b. it is completed as quickly as a simulation or emulation has begun.

As noted above with a view to generate acceptable HDL code they need to create inside graph representation of the assertion expression. The introduced example is awfully basic, so the graph to represent it's also very standard. all over the 1st step of its creation two graphs representing every of the sequences a and b are created. every of them has two states connected with and facet labeled appropriately with symbols a and b (representing associated sequences).

based on the graph building suggestions described in [2] the concatenation image „ ; ” suggests necessity of connecting both graph in such a method that the edge connecting the preliminary state of the 2d graph with its remaining state is copied and anchored in the ultimate state of the first graph. After optimization they get hold of the graph proven in the Fig. 1.

Fig 1. Graph representing fact assert a ; b

The interpretation of the graph is as follows: If state 2 turns into ”1” when the reset sign is inactive that capability that the statement reviews that the required situation is met.

The closing stage of the system of converting assertions into synthesizable RTL is genuine HDL era in accordance with the graph described. The outcomes is shown in Fig 2. during this code sign i[0] represents the sequence a; i[1] represents the sequence b and the sign o represents the price of the assertion (its “output”).

Fig 2. Verilog code implementing performance of assertion assert a ; b

example 2

The second example is a bit extra complicated:

assert on no account a;b[*] : c[*];d ; e

objects b[*] i c[*] symbolize based on PSL syntax sequences of b and c, that may also ensue any number of instances or may additionally now not take place.

Fig.3 Graphs representing the following expressions: a, b[*], c[*], d, e

The atomic graphs are concatenated (as the respective items in the analyzed assertions are certain with concatenation operator). because the first step they generate graphs representing expressions in braces. The effect of concatenation of graphs a and b is shown in Fig. three:

Fig 4. outcomes of concatenation of graphs a and b

The graph above may well be further transformed to minimize the number of states. although, for the sake of clarity the authors don't need to deviate from the direct outcomes of concatenation of the algorithm as represented with respective pseudocode in [2]. After the fusion of graphs representing the clauses contained in the interior braces of the analyzed assertion they acquire the graph in Fig. 5. in the statement syntax the mixture of graphs by using fusion algorithm is indicated by using image ”:”.

The remaining item in the analyzed statement is e and is preceded by means of the concatenation operator (;). hence the graph shown in Fig. 5 should still be concatenated with the graph e (shown in Fig. 3). After allowing for the note certainly not (we add the loop authentic in the state 1) they grow to be with the graph proven in Fig. 6.

Fig 5. Fusion algorithm influence

Fig.6 ultimate graph representingthe instance PSL statement

The graph in fig 6. should be received after optimization, however optimization algorithms have not been carried out yet through us. The graph generated from the fact without any optimization is shown in fig. 7. It will also be considered that useless states or unreachable states may additionally turn up right through execution of the algorithms that derive the graph from fact.

The graph can also be implemented in hardware (as a Hardware Checker). The implementation of such circuit is simple. They assign a single D flip-flop to each state of the graph and the excitation function for that flip-flop is derived from logic expressions linked to the sides going into that state. it's then very easy to generate illustration of such circuit within the hardware description language (Verilog in their instance).

To amplify, click on here

Fig. 7 Graph derived from the analyzed fact with the MBAC algorithms [2]

Flip-flops are usually grouped into registers. The flip-flop on probably the most significant bit is representing the output of the statement. Hardware Checker is synchronous and has synchronous reset. Verilog description of the Hardware Checker for the graph in fig. 7 is as follows.

module checker(clk,rst,i,o);

parameter I_WIDTH = 6;parameter X_WIDTH = 15;parameter S_WIDTH = sixteen;

enter clk;enter rst;enter [I_WIDTH - 1:0] i;output o;

localparam INIT = 6'b0000000000000001;

reg [S_WIDTH - 1:0] s;

wire [X_WIDTH - 1:0] x;wire [S_WIDTH - 1:0] n;

always @(posedge clk or posedge rst)if (rst)s <= INIT;elses <= n;

assign x[0] = i[0];assign x[1] = i[1];assign x[2] = i[2];assign x[3] = i[3];assign x[4] = i[4];

assign x[5] = i[1] & i[3];assign x[6] = i[1] & i[4];assign x[7] = i[2] & i[3];assign x[8] = i[2] & i[4];assign x[9] = i[5];assign x[10] = i[0] & i[1];assign x[11] = i[0] & i[1] & i[3];assign x[12] = i[0] & i[1] & i[4];assign x[13] = ~i[0];assign x[14] = i[0] & i[5];assign n[0] = 1'b0;assign n[1] = s[0] & x[0];assign n[2] = s[1] & x[0] | s[2] & x[0];assign n[3] = s[1] & x[0] | s[2] & x[0]; assign n[4] = 1'b0;assign n[5] = s[0] & x[10] | s[1] & x[10] | s[2] & x[10] | s[4] & x[1];assign n[6] = s[5] & x[2] | s[6] & x[2];assign n[7] = s[5] & x[2] | s[6] & x[2];assign n[8] = s[0] & x[11] | s[1] & x[11] | s[2] & x[11] | s[4] & x[5] | s[5] & x[7] | s[6] & x[7] | s[8] & x[3];assign n[9] = s[0] & x[11] | s[1] & x[11] | s[2] & x[11] | s[4] & x[5] | s[5] & x[7] | s[6] & x[7] | s[8] & x[3];assign n[10] = 1'b0;assign n[11] = s[0] & x[12] | s[1] & x[12] | s[2] & x[12] | s[4] & x[6] | s[5] & x[8] | s[6] & x[8] | s[8] & x[4] | s[9] & x[4] | s[10] & x[4];assign n[12] = 1'b0;assign n[13] = s[11] & x[9] | s[12] & x[9];assign n[14] = 1'b0;assign n[15] = s[11] & x[14] | s[12] & x[14] | s[14] & x[0];assign o = ~rst & (s[15]);

endmodule

in the Verilog code above the literal e from the analysed assertion is represented by i[5], d is represented via i[4], c through i[3], b through i[2], a by using i[1] and 1'b1 is saved in i[0].

CONCLUSIONS

For some categories of purposeful blocks (IP cores) hardware assisted verification has to enrich simulation within the manner of practical verification because of extreme simulation instances.

interaction of the hardware prototype with long-established utility testbench makes using the equal look at various fits in simulation and hardware assisted verification more straightforward.

Synthesizable assertions allow more straightforward places of errors found right through hardware assisted verification.

utility of these tactics to the verification of JPEG 2000 encoder proved viability of those ideas and resulted in up 300x shorter examine execution instances in regression checking out.

LITERATURE

[1] H. Foster, A. Krolnik, D.Lacey.: assertion based mostly Design, Kluwer tutorial Publishers, 2003

[2] M. Boule, Z. Zilic.: generating Hardware statement Checkers, Springer Verlag, 2008

[3] person’s manual. FoCs - Formal Checkers - a productiveness tool, ver 1.0, IBM research Lab in Haifa, April 2003

[4] A. Koczor, W. Sakowski, SystemC library aiding OVM compliant verification methodology, lawsuits of IP SoC 2011 conference, Grenoble, France, December 2011

[5] I. Sobanski, W. Sakowski, Verification of USB 3.0 device IP Core in Multi-Layer SystemC in proceedings of IP-ESC 2009 conference, Grenoble, France, 1-2 December 2009

[6] commonplace Co-Emulation Modeling Interface, unencumber 2.1, Acellera, 2011

[7] Property Specification Language Reference manual, edition 1.1, Accellera, 2004


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